mirror of https://github.com/YosysHQ/yosys.git
12 lines
152 B
Plaintext
12 lines
152 B
Plaintext
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read_verilog <<EOT
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module foo(inout a, b);
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assign a = b;
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endmodule
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module bar(output c);
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foo f(c, 1'b0);
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endmodule
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EOT
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hierarchy -auto-top
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flatten
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