mirror of https://github.com/YosysHQ/yosys.git
16 lines
182 B
Verilog
16 lines
182 B
Verilog
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module d_latch_gates(d,clk,q,q_bar);
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input d,clk;
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output q, q_bar;
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wire n1,n2,n3;
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not (n1,d);
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nand (n2,d,clk);
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nand (n3,n1,clk);
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nand (q,q_bar,n2);
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nand (q_bar,q,n3);
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endmodule
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