mirror of https://github.com/YosysHQ/yosys.git
104 lines
3.3 KiB
C++
104 lines
3.3 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2012 Martin Schmölzer <martin@schmoelzer.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/celltypes.h"
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#include "fsmdata.h"
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#include <string>
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#include <iostream>
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#include <fstream>
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/**
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* Convert signal into a KISS-compatible textual representation.
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*/
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std::string kiss_convert_signal(const RTLIL::SigSpec &sig) {
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if (!sig.is_fully_const()) {
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throw 0;
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}
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return sig.as_const().as_string();
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}
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/**
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* Exports each Finite State Machine (FSM) in the design to a file in KISS2 format.
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*/
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struct FsmExportPass : public Pass {
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FsmExportPass() : Pass("fsm_export") {
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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FsmData fsm_data;
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std::string kiss_name;
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std::ofstream kiss_file;
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size_t i;
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FsmData::transition_t tr;
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log_header("Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n");
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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for (auto &cell_it : mod_it.second->cells)
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if (cell_it.second->type == "$fsm") {
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kiss_name.assign(mod_it.first.c_str());
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kiss_name.append("-" + cell_it.second->name + ".kiss2");
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fsm_data.copy_from_cell(cell_it.second);
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log("\n");
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log("Exporting FSM `%s' from module `%s' to file `%s'.\n",
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cell_it.second->name.c_str(),
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mod_it.first.c_str(),
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kiss_name.c_str());
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kiss_file.open(kiss_name, std::ios::out | std::ios::trunc);
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if (!kiss_file.is_open()) {
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log_error("Could not open file \"%s\" with write access.\n", kiss_name.c_str());
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return;
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}
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kiss_file << ".start_kiss" << std::endl;
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kiss_file << ".i " << std::dec << fsm_data.num_inputs << std::endl;
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kiss_file << ".o " << std::dec << fsm_data.num_outputs << std::endl;
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kiss_file << ".r s" << std::dec << fsm_data.reset_state << std::endl;
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for (i = 0; i < fsm_data.transition_table.size(); i++) {
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tr = fsm_data.transition_table[i];
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try {
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kiss_file << kiss_convert_signal(tr.ctrl_in) << ' ';
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kiss_file << 's' << tr.state_in << ' ';
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kiss_file << 's' << tr.state_out << ' ';
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kiss_file << kiss_convert_signal(tr.ctrl_out) << std::endl;
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}
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catch (int) {
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log_error("exporting an FSM input or output signal failed.\n");
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}
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}
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kiss_file << ".end_kiss" << std::endl << ".end" << std::endl;
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kiss_file.close();
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}
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}
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} FsmExportPass;
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