mirror of https://github.com/YosysHQ/yosys.git
15 lines
527 B
Bash
15 lines
527 B
Bash
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#!/bin/bash
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set -ex
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if [ -z $ISE_DIR ]; then
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ISE_DIR=/opt/Xilinx/ISE/14.7
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fi
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sed 's/DSP48 /DSP48_UUT /; /DSP48_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp48_model_uut.v
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if [ ! -f "test_dsp48_model_ref.v" ]; then
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cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48.v test_dsp48_model_ref.v
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fi
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for tb in mult_allreg mult_noreg mult_inreg
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do
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iverilog -s $tb -s glbl -o test_dsp48_model test_dsp48_model.v test_dsp48_model_uut.v test_dsp48_model_ref.v $ISE_DIR/ISE_DS/ISE/verilog/src/glbl.v
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vvp -N ./test_dsp48_model
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done
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