mirror of https://github.com/YosysHQ/yosys.git
31 lines
578 B
Verilog
31 lines
578 B
Verilog
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module RAM_LUT(
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input [3:0] PORT_R_ADDR,
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input [3:0] PORT_RW_ADDR,
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input PORT_RW_CLK,
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input PORT_RW_WR_EN,
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input [3:0] PORT_RW_WR_DATA,
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output [3:0] PORT_R_RD_DATA,
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output [3:0] PORT_RW_RD_DATA
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);
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parameter INIT = 0;
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parameter PORT_RW_CLK_POL = 1;
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reg [3:0] mem [0:15];
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integer i;
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initial
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for (i = 0; i < 16; i += 1)
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mem[i] = INIT[i*4+:4];
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assign PORT_R_RD_DATA = mem[PORT_R_ADDR];
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assign PORT_RW_RD_DATA = mem[PORT_RW_ADDR];
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wire CLK = PORT_RW_CLK ~^ PORT_RW_CLK_POL;
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always @(posedge CLK)
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if (PORT_RW_WR_EN)
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mem[PORT_RW_ADDR] <= PORT_RW_WR_DATA;
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endmodule
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