mirror of https://github.com/YosysHQ/yosys.git
26 lines
334 B
Plaintext
26 lines
334 B
Plaintext
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read_verilog <<EOT
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module ff(...);
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input d;
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output q;
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endmodule
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module top(...);
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input d;
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output q1;
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(* init = 1'b1 *)
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output q2;
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ff my_ff1(.d(d), .q(q1));
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ff my_ff2(.d(d), .q(q2));
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endmodule
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EOT
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dffinit -ff ff q init
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select -assert-count 2 t:ff
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select -assert-count 1 t:ff r:init %i
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select -assert-count 1 t:ff r:init=1'b1 %i
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