mirror of https://github.com/YosysHQ/yosys.git
49 lines
1.2 KiB
Coq
49 lines
1.2 KiB
Coq
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// test case taken from amber23 verilog code
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module a23_barrel_shift_fpga_rotate(i_in, direction, shift_amount, rot_prod);
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input [31:0] i_in;
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input direction;
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input [4:0] shift_amount;
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output [31:0] rot_prod;
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// Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs.
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// Practically a bit higher due to high fanout of "direction".
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generate
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genvar i, j;
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for (i = 0; i < 5; i = i + 1)
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begin : netgen
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wire [31:0] in;
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reg [31:0] out;
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for (j = 0; j < 32; j = j + 1)
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begin : net
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always @*
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out[j] = in[j] & (~shift_amount[i] ^ direction) |
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in[wrap(j, i)] & (shift_amount[i] ^ direction);
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end
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end
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// Order is reverted with respect to volatile shift_amount[0]
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assign netgen[4].in = i_in;
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for (i = 1; i < 5; i = i + 1)
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begin : router
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assign netgen[i-1].in = netgen[i].out;
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end
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endgenerate
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// Aliasing
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assign rot_prod = netgen[0].out;
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function [4:0] wrap;
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input integer pos;
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input integer level;
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integer out;
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begin
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out = pos - (1 << level);
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wrap = out[4:0];
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end
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endfunction
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endmodule
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