mirror of https://github.com/YosysHQ/yosys.git
12 lines
511 B
Plaintext
12 lines
511 B
Plaintext
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read_verilog ../common/logic.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-count 6 t:MISTRAL_ALUT2
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select -assert-count 2 t:MISTRAL_ALUT4
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
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