2019-10-18 05:19:59 -05:00
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read_verilog ../common/mul.v
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2019-08-21 13:52:07 -05:00
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hierarchy -top top
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2019-12-31 20:40:11 -06:00
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equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
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2019-08-21 13:52:07 -05:00
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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2019-08-22 14:17:25 -05:00
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select -assert-count 1 t:SB_MAC16
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select -assert-none t:SB_MAC16 %% t:* %D
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