mirror of https://github.com/YosysHQ/yosys.git
23 lines
414 B
Plaintext
23 lines
414 B
Plaintext
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# https://github.com/yosyshq/yosys/issues/2035
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read_ilang <<END
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module \top
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wire width 1 input 0 \halfbrite
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wire width 2 output 1 \r_on
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process $1
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assign \r_on [1:0] 2'00
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assign \r_on [1:0] 2'11
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switch \halfbrite [0]
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case 1'1
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assign \r_on [1] 1'0
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end
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end
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end
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END
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proc_prune
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write_verilog assign_to_reg.v
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design -reset
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logger -expect-no-warnings
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read_verilog assign_to_reg.v
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