yosys/techlibs/machxo2/lutrams.txt

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2022-03-05 20:43:13 -06:00
ram distributed $__DPR16X4C_ {
abits 4;
width 4;
cost 4;
init no_undef;
prune_rom;
port sw "W" {
clock posedge;
}
port ar "R" {
}
}