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yosys/tests/arch/intel_alm/lutram.ys

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intel_alm: direct LUTRAM cell instantiation By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
2020-04-16 06:24:04 -05:00
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
proc
memory -nomap
intel_alm: Add global buffer insertion Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 08:34:48 -05:00
equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad -noclkbuf
intel_alm: direct LUTRAM cell instantiation By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
2020-04-16 06:24:04 -05:00
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
intel_alm: add Cyclone 10 GX tests
2020-07-05 12:53:14 -05:00
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
intel_alm: direct LUTRAM cell instantiation By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
2020-04-16 06:24:04 -05:00
design -load postopt
cd lutram_1w1r
select -assert-count 16 t:MISTRAL_MLAB
select -assert-count 2 t:MISTRAL_ALUT2
select -assert-count 8 t:MISTRAL_ALUT3
memory_bram: Reuse extract_rdff helper for make_outreg. Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
2021-05-25 12:31:53 -05:00
select -assert-count 8 t:MISTRAL_FF
select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
intel_alm: direct LUTRAM cell instantiation By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
2020-04-16 06:24:04 -05:00
intel_alm: add Cyclone 10 GX tests
2020-07-05 12:53:14 -05:00
design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
proc
memory -nomap
intel_alm: Add global buffer insertion Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 08:34:48 -05:00
equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad -noclkbuf
intel_alm: add Cyclone 10 GX tests
2020-07-05 12:53:14 -05:00
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
select -assert-count 16 t:MISTRAL_MLAB
select -assert-count 2 t:MISTRAL_ALUT2
select -assert-count 8 t:MISTRAL_ALUT3
memory_bram: Reuse extract_rdff helper for make_outreg. Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
2021-05-25 12:31:53 -05:00
select -assert-count 8 t:MISTRAL_FF
select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
intel_alm: drop quartus support
2024-05-03 05:16:34 -05:00