mirror of https://github.com/YosysHQ/yosys.git
193 lines
9.9 KiB
Coq
193 lines
9.9 KiB
Coq
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//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the authors nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: omsp_clock_mux.v
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//
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// *Module Description:
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// Standard clock mux for the openMSP430
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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//----------------------------------------------------------------------------
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module omsp_clock_mux (
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// OUTPUTs
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clk_out, // Clock output
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// INPUTs
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clk_in0, // Clock input 0
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clk_in1, // Clock input 1
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reset, // Reset
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scan_mode, // Scan mode (clk_in0 is selected in scan mode)
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select // Clock selection
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);
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// OUTPUTs
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//=========
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output clk_out; // Clock output
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// INPUTs
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//=========
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input clk_in0; // Clock input 0
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input clk_in1; // Clock input 1
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input reset; // Reset
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input scan_mode; // Scan mode (clk_in0 is selected in scan mode)
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input select; // Clock selection
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//===========================================================================================================================//
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// 1) CLOCK MUX //
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//===========================================================================================================================//
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// //
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// The following (glitch free) clock mux is implemented as following: //
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// //
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// //
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// //
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// //
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// +-----. +--------+ +--------+ //
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// select >>----+-------------O| \ | | | | +-----. //
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// | | |---| D Q |---| D Q |--+-------| \ //
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// | +-------O| / | | | | | | |O-+ //
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// | | +-----' | | | | | +--O| / | //
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// | | | /\ | | /\ | | | +-----' | //
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// | | +--+--+--+ +--+--+--+ | | | //
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// | | O | | | | //
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// | | | | | | | +-----. //
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// clk_in0 >>----------------------------------+------------+-----------+ +--| \ //
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// | | | | |----<< clk_out //
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// | | +---------------------------------------+ +--| / //
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// | | | | +-----' //
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// | +---------------------------------------------+ | //
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// | | | | //
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// | | +-----. +--------+ +--------+ | | //
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// | +-O| \ | | | | | +-----. | //
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// | | |---| D Q |---| D Q |--+-------| \ | //
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// +--------------| / | | | | | |O-+ //
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// +-----' | | | | +--O| / //
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// | /\ | | /\ | | +-----' //
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// +--+--+--+ +--+--+--+ | //
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// O | | //
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// | | | //
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// clk_in1 >>----------------------------------+------------+-----------+ //
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// //
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// //
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//===========================================================================================================================//
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//-----------------------------------------------------------------------------
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// Wire declarations
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//-----------------------------------------------------------------------------
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wire in0_select;
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reg in0_select_s;
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reg in0_select_ss;
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wire in0_enable;
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wire in1_select;
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reg in1_select_s;
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reg in1_select_ss;
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wire in1_enable;
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wire clk_in0_inv;
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wire clk_in1_inv;
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wire gated_clk_in0;
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wire gated_clk_in1;
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//-----------------------------------------------------------------------------
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// CLK_IN0 Selection
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//-----------------------------------------------------------------------------
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assign in0_select = ~select & ~in1_select_ss;
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always @ (posedge clk_in0_inv or posedge reset)
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if (reset) in0_select_s <= 1'b1;
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else in0_select_s <= in0_select;
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always @ (posedge clk_in0 or posedge reset)
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if (reset) in0_select_ss <= 1'b1;
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else in0_select_ss <= in0_select_s;
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assign in0_enable = in0_select_ss | scan_mode;
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//-----------------------------------------------------------------------------
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// CLK_IN1 Selection
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//-----------------------------------------------------------------------------
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assign in1_select = select & ~in0_select_ss;
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always @ (posedge clk_in1_inv or posedge reset)
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if (reset) in1_select_s <= 1'b0;
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else in1_select_s <= in1_select;
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always @ (posedge clk_in1 or posedge reset)
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if (reset) in1_select_ss <= 1'b0;
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else in1_select_ss <= in1_select_s;
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assign in1_enable = in1_select_ss & ~scan_mode;
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//-----------------------------------------------------------------------------
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// Clock MUX
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//-----------------------------------------------------------------------------
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//
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// IMPORTANT NOTE:
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// Because the clock network is a critical part of the design,
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// the following combinatorial logic should be replaced with
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// direct instanciation of standard cells from target library.
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// Don't forget the "dont_touch" attribute to make sure
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// synthesis won't mess it up.
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//
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// Replace with standard cell INVERTER
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assign clk_in0_inv = ~clk_in0;
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assign clk_in1_inv = ~clk_in1;
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// Replace with standard cell NAND2
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assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
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assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
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// Replace with standard cell AND2
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assign clk_out = (gated_clk_in0 & gated_clk_in1);
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endmodule // omsp_clock_gate
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