mirror of https://github.com/YosysHQ/yosys.git
23 lines
334 B
Coq
23 lines
334 B
Coq
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module test(in, out, clk, reset);
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input in, reset;
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output reg out;
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input clk;
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reg signed [3:0] a;
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reg signed [3:0] b;
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reg signed [3:0] c;
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reg [5:0] d;
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reg [5:0] e;
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always @(clk or reset) begin
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a = -4;
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b = 2;
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c = a + b;
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d = a + b + c;
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d = d*d;
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if(b)
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e = d*d;
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else
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e = d + d;
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end
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endmodule
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