mirror of https://github.com/YosysHQ/yosys.git
13 lines
190 B
Verilog
13 lines
190 B
Verilog
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module counter (clk, rst, en, count);
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input clk, rst, en;
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output reg [1:0] count;
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always @(posedge clk)
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if (rst)
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count <= 2'd0;
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else if (en)
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count <= count + 2'd1;
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endmodule
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