mirror of https://github.com/YosysHQ/yosys.git
10 lines
396 B
Plaintext
10 lines
396 B
Plaintext
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read_verilog add_sub.v
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hierarchy -top top
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 11 t:SB_LUT4
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select -assert-count 6 t:SB_CARRY
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select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
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