mirror of https://github.com/YosysHQ/yosys.git
13 lines
161 B
Plaintext
13 lines
161 B
Plaintext
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ram block \RAM_WIDE_READ {
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cost 2;
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abits 6;
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widths 1 2 4 8 per_port;
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init any;
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port srsw "A" {
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width rd 8 wr 2;
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clock posedge;
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rden;
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rdwr old;
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}
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}
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