yosys/tests/verilog/unbased_unsized.ys

mirror of https://github.com/YosysHQ/yosys.git
read_verilog -sv unbased_unsized.sv
hierarchy
proc
flatten
opt -full
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sv: fix some edge cases for unbased unsized literals - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst` 2021-03-03 13:36:19 -06:00			`read_verilog -sv unbased_unsized.sv`
			`hierarchy`
			`proc`
			`flatten`
			`opt -full`
			`select -module top`
			`sat -verify -seq 1 -tempinduct -prove-asserts -show-all`