mirror of https://github.com/YosysHQ/yosys.git
43 lines
790 B
Verilog
43 lines
790 B
Verilog
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module lutram_1w1r
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#(parameter D_WIDTH=8, A_WIDTH=6)
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(
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input [D_WIDTH-1:0] data_a,
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input [A_WIDTH:1] addr_a,
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input we_a, clk,
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output reg [D_WIDTH-1:0] q_a
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);
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// Declare the RAM variable
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reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];
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// Port A
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always @ (posedge clk)
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begin
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if (we_a)
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ram[addr_a] <= data_a;
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q_a <= ram[addr_a];
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end
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endmodule
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module lutram_1w3r
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#(parameter D_WIDTH=8, A_WIDTH=5)
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(
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input [D_WIDTH-1:0] data_a, data_b, data_c,
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input [A_WIDTH:1] addr_a, addr_b, addr_c,
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input we_a, clk,
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output reg [D_WIDTH-1:0] q_a, q_b, q_c
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);
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// Declare the RAM variable
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reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];
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// Port A
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always @ (posedge clk)
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begin
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if (we_a)
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ram[addr_a] <= data_a;
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q_a <= ram[addr_a];
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q_b <= ram[addr_b];
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q_c <= ram[addr_c];
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end
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endmodule
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