mirror of https://github.com/YosysHQ/yosys.git
77 lines
2.4 KiB
C++
77 lines
2.4 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SupercoverPass : public Pass {
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SupercoverPass() : Pass("supercover", "add hi/lo cover cells for each wire bit") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" supercover [options] [selection]\n");
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log("\n");
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log("This command adds two cover cells for each bit of each selected wire, one\n");
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log("checking for a hi signal level and one checking for lo level.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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// bool flag_noinit = false;
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log_header(design, "Executing SUPERCOVER pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-noinit") {
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// flag_noinit = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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int cnt_wire = 0, cnt_bits = 0;
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log("Adding cover cells to module %s.\n", log_id(module));
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for (auto wire : module->selected_wires())
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{
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std::string src = wire->get_src_attribute();
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cnt_wire++;
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for (auto bit : SigSpec(wire))
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{
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SigSpec inv = module->Not(NEW_ID, bit);
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module->addCover(NEW_ID, bit, State::S1, src);
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module->addCover(NEW_ID, inv, State::S1, src);
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cnt_bits++;
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}
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}
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log(" added cover cells to %d wires, %d bits.\n", cnt_wire, cnt_bits);
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}
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}
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} SupercoverPass;
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PRIVATE_NAMESPACE_END
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