mirror of https://github.com/YosysHQ/yosys.git
19 lines
769 B
Plaintext
19 lines
769 B
Plaintext
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read_verilog ../common/counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -assert -multiclock -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT1
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select -assert-count 5 t:LUT2
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select -assert-count 2 t:LUT3
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select -assert-count 3 t:LUT4
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select -assert-count 8 t:dffepc
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 8 t:outpad
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select -assert-count 2 t:ckpad
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select -assert-none t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:dffepc t:logic_0 t:logic_1 t:outpad t:ckpad %% t:* %D
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