2013-01-05 04:13:26 -06:00
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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2015-07-02 04:14:30 -05:00
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*
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2013-01-05 04:13:26 -06:00
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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2015-07-02 04:14:30 -05:00
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*
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2013-01-05 04:13:26 -06:00
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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2014-07-30 15:04:30 -05:00
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#include "kernel/yosys.h"
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2014-08-16 17:55:35 -05:00
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#include "kernel/utils.h"
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2014-07-30 15:04:30 -05:00
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#include "kernel/sigtools.h"
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#include "libs/sha1/sha1.h"
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2013-01-05 04:13:26 -06:00
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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2014-12-24 03:49:24 -06:00
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#include "simplemap.h"
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2014-07-30 19:32:00 -05:00
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#include "passes/techmap/techmap.inc"
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2013-01-05 04:13:26 -06:00
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2014-09-27 09:17:53 -05:00
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YOSYS_NAMESPACE_BEGIN
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2014-09-07 11:23:37 -05:00
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// see maccmap.cc
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extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false);
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2014-09-27 09:17:53 -05:00
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YOSYS_NAMESPACE_END
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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2019-08-15 12:19:29 -05:00
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void apply_prefix(IdString prefix, IdString &id)
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2013-01-05 04:13:26 -06:00
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{
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if (id[0] == '\\')
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2019-08-15 12:19:29 -05:00
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id = stringf("%s.%s", prefix.c_str(), id.c_str()+1);
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2013-01-05 04:13:26 -06:00
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else
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2019-08-15 12:19:29 -05:00
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id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str());
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2013-01-05 04:13:26 -06:00
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}
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2019-08-15 12:19:29 -05:00
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void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
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2013-01-05 04:13:26 -06:00
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{
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2015-10-24 12:09:45 -05:00
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vector<SigChunk> chunks = sig;
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2014-07-23 08:36:09 -05:00
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for (auto &chunk : chunks)
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if (chunk.wire != NULL) {
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2019-08-15 12:19:29 -05:00
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IdString wire_name = chunk.wire->name;
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2014-07-23 08:36:09 -05:00
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apply_prefix(prefix, wire_name);
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2014-07-28 04:08:55 -05:00
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log_assert(module->wires_.count(wire_name) > 0);
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2014-07-26 18:49:51 -05:00
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chunk.wire = module->wires_[wire_name];
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2014-07-23 08:36:09 -05:00
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}
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sig = chunks;
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2013-01-05 04:13:26 -06:00
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}
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2014-02-16 10:16:44 -06:00
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struct TechmapWorker
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{
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2014-08-02 06:11:01 -05:00
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std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
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2014-02-16 10:16:44 -06:00
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std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
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std::map<RTLIL::Module*, bool> techmap_do_cache;
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2014-08-02 09:03:18 -05:00
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std::set<RTLIL::Module*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Module>> module_queue;
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2015-02-21 04:21:28 -06:00
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dict<Module*, SigMap> sigmaps;
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2013-01-05 04:13:26 -06:00
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2015-02-25 05:46:00 -06:00
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pool<IdString> flatten_do_list;
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pool<IdString> flatten_done_list;
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pool<Cell*> flatten_keep_list;
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2019-04-22 10:25:52 -05:00
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pool<string> log_msg_cache;
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2014-02-16 10:16:44 -06:00
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struct TechmapWireData {
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RTLIL::Wire *wire;
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RTLIL::SigSpec value;
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};
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2013-11-23 08:58:06 -06:00
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2014-02-16 10:16:44 -06:00
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typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
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2013-11-23 08:58:06 -06:00
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2014-07-30 19:21:41 -05:00
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bool extern_mode;
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bool assert_mode;
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bool flatten_mode;
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2014-08-03 05:40:43 -05:00
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bool recursive_mode;
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2014-09-01 08:36:29 -05:00
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bool autoproc_mode;
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2019-04-18 12:19:45 -05:00
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bool ignore_wb;
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2014-07-30 19:21:41 -05:00
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TechmapWorker()
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{
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extern_mode = false;
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assert_mode = false;
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flatten_mode = false;
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2014-08-03 05:40:43 -05:00
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recursive_mode = false;
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2014-09-01 08:36:29 -05:00
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autoproc_mode = false;
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2019-04-18 12:19:45 -05:00
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ignore_wb = false;
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2014-07-30 19:21:41 -05:00
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}
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2014-07-30 15:04:30 -05:00
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std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
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{
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std::string constmap_info;
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2014-08-02 06:11:01 -05:00
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std::map<RTLIL::SigBit, std::pair<RTLIL::IdString, int>> connbits_map;
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2014-07-30 15:04:30 -05:00
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for (auto conn : cell->connections())
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2014-10-10 09:59:44 -05:00
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for (int i = 0; i < GetSize(conn.second); i++) {
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2014-07-30 15:04:30 -05:00
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RTLIL::SigBit bit = sigmap(conn.second[i]);
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if (bit.wire == nullptr) {
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if (verbose)
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log(" Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit));
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constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data);
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} else if (connbits_map.count(bit)) {
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if (verbose)
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log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first),
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connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
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constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
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log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
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2014-10-10 10:22:08 -05:00
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} else {
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connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);
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constmap_info += stringf("|%s %d", log_id(conn.first), i);
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}
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2014-07-30 15:04:30 -05:00
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}
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2014-08-01 12:01:10 -05:00
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return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
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2014-07-30 15:04:30 -05:00
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}
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2014-02-16 10:16:44 -06:00
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TechmapWires techmap_find_special_wires(RTLIL::Module *module)
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{
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TechmapWires result;
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2013-03-28 04:12:50 -05:00
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2014-02-16 10:16:44 -06:00
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if (module == NULL)
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return result;
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2013-03-28 04:12:50 -05:00
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2014-07-26 18:49:51 -05:00
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for (auto &it : module->wires_) {
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2014-02-16 10:16:44 -06:00
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const char *p = it.first.c_str();
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if (*p == '$')
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continue;
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2013-11-23 08:58:06 -06:00
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2014-02-16 10:16:44 -06:00
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const char *q = strrchr(p+1, '.');
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2015-01-15 06:36:57 -06:00
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p = q ? q+1 : p+1;
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2013-11-23 08:58:06 -06:00
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2014-02-16 10:16:44 -06:00
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if (!strncmp(p, "_TECHMAP_", 9)) {
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TechmapWireData record;
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record.wire = it.second;
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record.value = it.second;
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result[p].push_back(record);
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2019-08-15 16:51:12 -05:00
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it.second->attributes[ID::keep] = RTLIL::Const(1);
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2019-08-15 12:25:54 -05:00
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it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1);
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2014-02-16 10:16:44 -06:00
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}
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2013-11-23 08:58:06 -06:00
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}
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2013-03-28 04:12:50 -05:00
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2014-02-16 10:16:44 -06:00
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if (!result.empty()) {
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SigMap sigmap(module);
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for (auto &it1 : result)
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for (auto &it2 : it1.second)
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sigmap.apply(it2.value);
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}
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2013-03-28 04:12:50 -05:00
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2014-02-16 10:16:44 -06:00
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return result;
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2013-03-28 04:12:50 -05:00
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}
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2014-07-30 19:21:41 -05:00
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void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
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2014-02-16 10:16:44 -06:00
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{
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2014-05-26 10:13:41 -05:00
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if (tpl->processes.size() != 0) {
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2015-07-18 05:16:27 -05:00
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log("Technology map yielded processes:");
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2014-05-26 10:13:41 -05:00
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for (auto &it : tpl->processes)
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2015-07-18 05:16:27 -05:00
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log(" %s",RTLIL::id2cstr(it.first));
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log("\n");
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2014-09-01 08:36:29 -05:00
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if (autoproc_mode) {
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Pass::call_on_module(tpl->design, tpl, "proc");
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2014-10-10 09:59:44 -05:00
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log_assert(GetSize(tpl->processes) == 0);
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2014-09-01 08:36:29 -05:00
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} else
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log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
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2014-05-26 10:13:41 -05:00
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}
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2014-02-16 10:16:44 -06:00
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2014-02-20 16:42:07 -06:00
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std::string orig_cell_name;
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2019-08-15 12:25:54 -05:00
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pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src));
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2015-04-24 15:04:05 -05:00
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2020-03-23 05:07:03 -05:00
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orig_cell_name = cell->name.str();
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2018-03-10 06:55:30 -06:00
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if (!flatten_mode) {
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2014-07-26 18:51:45 -05:00
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for (auto &it : tpl->cells_)
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2019-08-15 12:25:54 -05:00
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if (it.first == ID(_TECHMAP_REPLACE_)) {
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2014-08-02 06:11:01 -05:00
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module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
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2014-02-20 16:42:07 -06:00
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break;
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}
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2015-04-24 15:04:05 -05:00
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}
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2015-01-17 13:46:52 -06:00
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dict<IdString, IdString> memory_renames;
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for (auto &it : tpl->memories) {
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2019-08-15 12:19:29 -05:00
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IdString m_name = it.first;
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apply_prefix(cell->name, m_name);
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2015-01-17 13:46:52 -06:00
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RTLIL::Memory *m = new RTLIL::Memory;
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m->name = m_name;
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m->width = it.second->width;
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m->start_offset = it.second->start_offset;
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m->size = it.second->size;
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m->attributes = it.second->attributes;
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2019-08-15 12:25:54 -05:00
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if (m->attributes.count(ID(src)))
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m->add_strpool_attribute(ID(src), extra_src_attrs);
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2015-01-17 13:46:52 -06:00
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module->memories[m->name] = m;
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memory_renames[it.first] = m->name;
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design->select(module, m);
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}
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2014-02-16 10:16:44 -06:00
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std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
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2019-09-05 06:51:53 -05:00
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dict<Wire*, IdString> temp_renamed_wires;
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2019-09-19 12:26:09 -05:00
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pool<SigBit> autopurge_tpl_bits;
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2014-02-16 10:16:44 -06:00
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2019-09-19 12:26:09 -05:00
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for (auto &it : tpl->wires_)
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{
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2014-02-16 10:16:44 -06:00
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if (it.second->port_id > 0)
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2019-09-19 12:26:09 -05:00
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{
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IdString posportname = stringf("$%d", it.second->port_id);
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positional_ports[posportname] = it.first;
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if (!flatten_mode && it.second->get_bool_attribute(ID(techmap_autopurge)) &&
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(!cell->hasPort(it.second->name) || !GetSize(cell->getPort(it.second->name))) &&
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(!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
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{
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if (sigmaps.count(tpl) == 0)
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sigmaps[tpl].set(tpl);
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for (auto bit : sigmaps.at(tpl)(it.second))
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if (bit.wire != nullptr)
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2019-09-20 19:42:36 -05:00
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autopurge_tpl_bits.insert(bit);
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2019-09-19 12:26:09 -05:00
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}
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}
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2019-08-15 12:19:29 -05:00
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IdString w_name = it.second->name;
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apply_prefix(cell->name, w_name);
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2019-08-26 17:55:43 -05:00
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RTLIL::Wire *w = module->wire(w_name);
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if (w != nullptr) {
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2019-09-05 06:51:53 -05:00
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if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) {
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temp_renamed_wires[w] = w->name;
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module->rename(w, NEW_ID);
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w = nullptr;
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} else {
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w->attributes.erase(ID(hierconn));
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if (GetSize(w) < GetSize(it.second)) {
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log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
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log_id(tpl), log_id(it.second), log_id(module), log_id(cell));
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w->width = GetSize(it.second);
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}
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2019-08-26 17:55:43 -05:00
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}
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2019-09-05 06:51:53 -05:00
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}
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if (w == nullptr) {
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2019-08-26 17:55:43 -05:00
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w = module->addWire(w_name, it.second);
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w->port_input = false;
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w->port_output = false;
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w->port_id = 0;
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2019-09-19 12:26:09 -05:00
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if (!flatten_mode)
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w->attributes.erase(ID(techmap_autopurge));
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2019-08-26 17:55:43 -05:00
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if (it.second->get_bool_attribute(ID(_techmap_special_)))
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w->attributes.clear();
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if (w->attributes.count(ID(src)))
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w->add_strpool_attribute(ID(src), extra_src_attrs);
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}
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2014-02-16 10:16:44 -06:00
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design->select(module, w);
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2019-09-30 19:20:12 -05:00
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|
|
|
if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) {
|
|
|
|
IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
|
|
|
|
Wire *replace_w = module->addWire(replace_name, it.second);
|
|
|
|
module->connect(replace_w, w);
|
|
|
|
}
|
2013-03-28 04:12:50 -05:00
|
|
|
}
|
2014-02-16 10:16:44 -06:00
|
|
|
|
2015-05-23 03:14:53 -05:00
|
|
|
SigMap tpl_sigmap(tpl);
|
|
|
|
pool<SigBit> tpl_written_bits;
|
|
|
|
|
|
|
|
for (auto &it1 : tpl->cells_)
|
|
|
|
for (auto &it2 : it1.second->connections_)
|
|
|
|
if (it1.second->output(it2.first))
|
|
|
|
for (auto bit : tpl_sigmap(it2.second))
|
|
|
|
tpl_written_bits.insert(bit);
|
|
|
|
for (auto &it1 : tpl->connections_)
|
|
|
|
for (auto bit : tpl_sigmap(it1.first))
|
|
|
|
tpl_written_bits.insert(bit);
|
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
SigMap port_signal_map;
|
2016-05-06 06:59:30 -05:00
|
|
|
SigSig port_signal_assign;
|
2014-02-16 10:16:44 -06:00
|
|
|
|
2016-05-06 06:59:30 -05:00
|
|
|
for (auto &it : cell->connections())
|
|
|
|
{
|
2014-02-16 10:16:44 -06:00
|
|
|
RTLIL::IdString portname = it.first;
|
|
|
|
if (positional_ports.count(portname) > 0)
|
|
|
|
portname = positional_ports.at(portname);
|
2014-07-26 18:49:51 -05:00
|
|
|
if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
|
2019-08-07 14:20:08 -05:00
|
|
|
if (portname.begins_with("$"))
|
2014-02-16 10:16:44 -06:00
|
|
|
log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
|
|
|
|
continue;
|
|
|
|
}
|
2016-05-06 06:59:30 -05:00
|
|
|
|
2017-07-21 12:32:31 -05:00
|
|
|
if (GetSize(it.second) == 0)
|
|
|
|
continue;
|
|
|
|
|
2014-07-26 18:49:51 -05:00
|
|
|
RTLIL::Wire *w = tpl->wires_.at(portname);
|
2016-05-06 06:59:30 -05:00
|
|
|
RTLIL::SigSig c, extra_connect;
|
|
|
|
|
2015-05-23 03:14:53 -05:00
|
|
|
if (w->port_output && !w->port_input) {
|
2014-02-16 10:16:44 -06:00
|
|
|
c.first = it.second;
|
|
|
|
c.second = RTLIL::SigSpec(w);
|
2019-08-15 12:19:29 -05:00
|
|
|
apply_prefix(cell->name, c.second, module);
|
2016-05-06 06:59:30 -05:00
|
|
|
extra_connect.first = c.second;
|
|
|
|
extra_connect.second = c.first;
|
2015-05-23 03:14:53 -05:00
|
|
|
} else if (!w->port_output && w->port_input) {
|
2014-02-16 10:16:44 -06:00
|
|
|
c.first = RTLIL::SigSpec(w);
|
|
|
|
c.second = it.second;
|
2019-08-15 12:19:29 -05:00
|
|
|
apply_prefix(cell->name, c.first, module);
|
2016-05-06 06:59:30 -05:00
|
|
|
extra_connect.first = c.first;
|
|
|
|
extra_connect.second = c.second;
|
2015-05-23 03:14:53 -05:00
|
|
|
} else {
|
|
|
|
SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second;
|
2019-08-15 12:19:29 -05:00
|
|
|
apply_prefix(cell->name, sig_tpl_pf, module);
|
2015-10-13 03:30:23 -05:00
|
|
|
for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) {
|
2015-05-23 03:14:53 -05:00
|
|
|
if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) {
|
|
|
|
c.first.append(sig_mod[i]);
|
|
|
|
c.second.append(sig_tpl_pf[i]);
|
|
|
|
} else {
|
|
|
|
c.first.append(sig_tpl_pf[i]);
|
|
|
|
c.second.append(sig_mod[i]);
|
|
|
|
}
|
|
|
|
}
|
2016-05-06 06:59:30 -05:00
|
|
|
extra_connect.first = sig_tpl_pf;
|
|
|
|
extra_connect.second = sig_mod;
|
2014-02-16 10:16:44 -06:00
|
|
|
}
|
2016-05-06 06:59:30 -05:00
|
|
|
|
2014-07-22 13:15:14 -05:00
|
|
|
if (c.second.size() > c.first.size())
|
|
|
|
c.second.remove(c.first.size(), c.second.size() - c.first.size());
|
2016-05-06 06:59:30 -05:00
|
|
|
|
2014-07-22 13:15:14 -05:00
|
|
|
if (c.second.size() < c.first.size())
|
|
|
|
c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
|
2016-05-06 06:59:30 -05:00
|
|
|
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(c.first.size() == c.second.size());
|
2016-05-06 06:59:30 -05:00
|
|
|
|
|
|
|
if (flatten_mode)
|
|
|
|
{
|
2014-02-17 02:44:39 -06:00
|
|
|
// more conservative approach:
|
|
|
|
// connect internal and external wires
|
2016-05-06 06:59:30 -05:00
|
|
|
|
2015-02-21 04:21:28 -06:00
|
|
|
if (sigmaps.count(module) == 0)
|
|
|
|
sigmaps[module].set(module);
|
2016-05-06 06:59:30 -05:00
|
|
|
|
2015-02-21 04:21:28 -06:00
|
|
|
if (sigmaps.at(module)(c.first).has_const())
|
|
|
|
log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
|
|
|
|
log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
|
2016-05-06 06:59:30 -05:00
|
|
|
|
2014-07-26 07:32:50 -05:00
|
|
|
module->connect(c);
|
2016-05-06 06:59:30 -05:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2014-02-17 02:44:39 -06:00
|
|
|
// approach that yields nicer outputs:
|
|
|
|
// replace internal wires that are connected to external wires
|
2016-05-06 06:59:30 -05:00
|
|
|
|
2017-02-13 09:55:25 -06:00
|
|
|
if (w->port_output && !w->port_input) {
|
2014-02-17 02:44:39 -06:00
|
|
|
port_signal_map.add(c.second, c.first);
|
2017-02-13 09:55:25 -06:00
|
|
|
} else
|
|
|
|
if (!w->port_output && w->port_input) {
|
2014-02-17 02:44:39 -06:00
|
|
|
port_signal_map.add(c.first, c.second);
|
2017-02-13 09:55:25 -06:00
|
|
|
} else {
|
|
|
|
module->connect(c);
|
|
|
|
extra_connect = SigSig();
|
|
|
|
}
|
2016-05-06 06:59:30 -05:00
|
|
|
|
|
|
|
for (auto &attr : w->attributes) {
|
2019-08-15 12:25:54 -05:00
|
|
|
if (attr.first == ID(src))
|
2016-05-06 06:59:30 -05:00
|
|
|
continue;
|
2019-09-20 19:48:37 -05:00
|
|
|
auto lhs = GetSize(extra_connect.first);
|
|
|
|
auto rhs = GetSize(extra_connect.second);
|
|
|
|
if (lhs > rhs)
|
|
|
|
extra_connect.first.remove(rhs, lhs-rhs);
|
|
|
|
else if (rhs > lhs)
|
|
|
|
extra_connect.second.remove(lhs, rhs-lhs);
|
2016-05-06 06:59:30 -05:00
|
|
|
module->connect(extra_connect);
|
|
|
|
break;
|
|
|
|
}
|
2014-02-17 02:44:39 -06:00
|
|
|
}
|
2014-02-16 10:16:44 -06:00
|
|
|
}
|
|
|
|
|
2014-07-26 18:51:45 -05:00
|
|
|
for (auto &it : tpl->cells_)
|
2014-07-25 08:05:18 -05:00
|
|
|
{
|
2019-08-15 12:19:29 -05:00
|
|
|
IdString c_name = it.second->name.str();
|
2019-08-15 12:25:54 -05:00
|
|
|
bool techmap_replace_cell = (!flatten_mode) && (c_name == ID(_TECHMAP_REPLACE_));
|
2014-07-25 08:05:18 -05:00
|
|
|
|
2017-02-16 05:28:42 -06:00
|
|
|
if (techmap_replace_cell)
|
2014-07-25 08:05:18 -05:00
|
|
|
c_name = orig_cell_name;
|
2019-10-02 14:43:35 -05:00
|
|
|
else if (it.second->name.begins_with("\\_TECHMAP_REPLACE_."))
|
|
|
|
c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
|
2014-02-20 16:42:07 -06:00
|
|
|
else
|
2019-08-15 12:19:29 -05:00
|
|
|
apply_prefix(cell->name, c_name);
|
2014-07-25 08:05:18 -05:00
|
|
|
|
2014-07-25 17:38:44 -05:00
|
|
|
RTLIL::Cell *c = module->addCell(c_name, it.second);
|
2014-07-25 08:05:18 -05:00
|
|
|
design->select(module, c);
|
|
|
|
|
2019-08-07 14:20:08 -05:00
|
|
|
if (!flatten_mode && c->type.begins_with("\\$"))
|
2014-07-25 17:38:44 -05:00
|
|
|
c->type = c->type.substr(1);
|
|
|
|
|
2019-09-19 12:26:09 -05:00
|
|
|
vector<IdString> autopurge_ports;
|
|
|
|
|
|
|
|
for (auto &it2 : c->connections_)
|
|
|
|
{
|
|
|
|
bool autopurge = false;
|
|
|
|
if (!autopurge_tpl_bits.empty()) {
|
|
|
|
autopurge = GetSize(it2.second) != 0;
|
|
|
|
for (auto &bit : sigmaps.at(tpl)(it2.second))
|
|
|
|
if (!autopurge_tpl_bits.count(bit)) {
|
|
|
|
autopurge = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (autopurge) {
|
|
|
|
autopurge_ports.push_back(it2.first);
|
|
|
|
} else {
|
|
|
|
apply_prefix(cell->name, it2.second, module);
|
|
|
|
port_signal_map.apply(it2.second);
|
|
|
|
}
|
2014-02-16 10:16:44 -06:00
|
|
|
}
|
2015-01-17 13:46:52 -06:00
|
|
|
|
2019-09-19 12:26:09 -05:00
|
|
|
for (auto &it2 : autopurge_ports)
|
|
|
|
c->unsetPort(it2);
|
|
|
|
|
2019-08-15 12:05:08 -05:00
|
|
|
if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
|
2019-08-15 12:25:54 -05:00
|
|
|
IdString memid = c->getParam(ID(MEMID)).decode_string();
|
2016-02-13 10:31:24 -06:00
|
|
|
log_assert(memory_renames.count(memid) != 0);
|
2019-08-15 12:25:54 -05:00
|
|
|
c->setParam(ID(MEMID), Const(memory_renames[memid].str()));
|
2015-01-17 13:46:52 -06:00
|
|
|
}
|
2015-04-24 15:04:05 -05:00
|
|
|
|
2019-08-15 12:05:08 -05:00
|
|
|
if (c->type == ID($mem)) {
|
2019-08-15 12:25:54 -05:00
|
|
|
IdString memid = c->getParam(ID(MEMID)).decode_string();
|
2019-08-15 12:19:29 -05:00
|
|
|
apply_prefix(cell->name, memid);
|
2019-08-15 12:25:54 -05:00
|
|
|
c->setParam(ID(MEMID), Const(memid.c_str()));
|
2016-10-14 03:36:37 -05:00
|
|
|
}
|
|
|
|
|
2019-08-15 12:25:54 -05:00
|
|
|
if (c->attributes.count(ID(src)))
|
|
|
|
c->add_strpool_attribute(ID(src), extra_src_attrs);
|
2017-02-16 05:28:42 -06:00
|
|
|
|
|
|
|
if (techmap_replace_cell)
|
|
|
|
for (auto attr : cell->attributes)
|
|
|
|
if (!c->attributes.count(attr.first))
|
|
|
|
c->attributes[attr.first] = attr.second;
|
2014-02-16 10:16:44 -06:00
|
|
|
}
|
2013-10-17 15:19:38 -05:00
|
|
|
|
2014-07-26 07:32:50 -05:00
|
|
|
for (auto &it : tpl->connections()) {
|
2014-02-16 10:16:44 -06:00
|
|
|
RTLIL::SigSig c = it;
|
2014-08-02 06:11:01 -05:00
|
|
|
apply_prefix(cell->name.str(), c.first, module);
|
|
|
|
apply_prefix(cell->name.str(), c.second, module);
|
2014-02-16 10:16:44 -06:00
|
|
|
port_signal_map.apply(c.first);
|
|
|
|
port_signal_map.apply(c.second);
|
2014-07-26 07:32:50 -05:00
|
|
|
module->connect(c);
|
2013-10-17 15:19:38 -05:00
|
|
|
}
|
|
|
|
|
2014-07-25 08:05:18 -05:00
|
|
|
module->remove(cell);
|
2019-09-05 06:51:53 -05:00
|
|
|
|
|
|
|
for (auto &it : temp_renamed_wires)
|
|
|
|
{
|
|
|
|
Wire *w = it.first;
|
|
|
|
IdString name = it.second;
|
|
|
|
IdString altname = module->uniquify(name);
|
|
|
|
Wire *other_w = module->wire(name);
|
|
|
|
module->rename(other_w, altname);
|
|
|
|
module->rename(w, name);
|
|
|
|
}
|
2013-03-28 04:12:50 -05:00
|
|
|
}
|
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
|
2014-08-14 19:40:46 -05:00
|
|
|
const std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
|
2014-02-16 10:16:44 -06:00
|
|
|
{
|
2014-08-03 05:40:43 -05:00
|
|
|
std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
|
|
|
|
|
2019-04-20 04:23:24 -05:00
|
|
|
if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
|
2014-02-16 10:16:44 -06:00
|
|
|
return false;
|
2013-03-28 04:12:50 -05:00
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
bool log_continue = false;
|
|
|
|
bool did_something = false;
|
2019-04-22 10:25:52 -05:00
|
|
|
LogMakeDebugHdl mkdebug;
|
2013-02-28 17:36:19 -06:00
|
|
|
|
2014-02-16 14:58:59 -06:00
|
|
|
SigMap sigmap(module);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2019-08-15 22:14:03 -05:00
|
|
|
dict<SigBit, State> init_bits;
|
|
|
|
pool<SigBit> remove_init_bits;
|
|
|
|
|
|
|
|
for (auto wire : module->wires()) {
|
|
|
|
if (wire->attributes.count("\\init")) {
|
|
|
|
Const value = wire->attributes.at("\\init");
|
|
|
|
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
|
|
|
|
if (value[i] != State::Sx)
|
|
|
|
init_bits[sigmap(SigBit(wire, i))] = value[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-07 08:21:03 -06:00
|
|
|
TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
|
2014-07-27 09:19:24 -05:00
|
|
|
std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
|
|
|
|
std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-07-27 09:19:24 -05:00
|
|
|
for (auto cell : module->cells())
|
|
|
|
{
|
2014-02-16 10:16:44 -06:00
|
|
|
if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
|
|
|
|
continue;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-08-03 05:40:43 -05:00
|
|
|
std::string cell_type = cell->type.str();
|
2019-08-07 14:20:08 -05:00
|
|
|
if (in_recursion && cell->type.begins_with("\\$"))
|
2014-08-03 05:40:43 -05:00
|
|
|
cell_type = cell_type.substr(1);
|
|
|
|
|
|
|
|
if (celltypeMap.count(cell_type) == 0) {
|
|
|
|
if (assert_mode && cell_type.back() != '_')
|
|
|
|
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
|
2014-02-16 10:16:44 -06:00
|
|
|
continue;
|
2014-07-30 19:21:41 -05:00
|
|
|
}
|
2013-02-28 17:36:19 -06:00
|
|
|
|
2015-02-25 05:46:00 -06:00
|
|
|
if (flatten_mode) {
|
2019-08-15 12:25:54 -05:00
|
|
|
bool keepit = cell->get_bool_attribute(ID(keep_hierarchy));
|
2015-02-25 05:46:00 -06:00
|
|
|
for (auto &tpl_name : celltypeMap.at(cell_type))
|
2019-08-15 12:25:54 -05:00
|
|
|
if (map->modules_[tpl_name]->get_bool_attribute(ID(keep_hierarchy)))
|
2015-02-25 05:46:00 -06:00
|
|
|
keepit = true;
|
|
|
|
if (keepit) {
|
|
|
|
if (!flatten_keep_list[cell]) {
|
|
|
|
log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell));
|
|
|
|
flatten_keep_list.insert(cell);
|
|
|
|
}
|
|
|
|
if (!flatten_done_list[cell->type])
|
|
|
|
flatten_do_list.insert(cell->type);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-27 09:19:24 -05:00
|
|
|
for (auto &conn : cell->connections())
|
|
|
|
{
|
|
|
|
RTLIL::SigSpec sig = sigmap(conn.second);
|
|
|
|
sig.remove_const();
|
|
|
|
|
2014-10-10 09:59:44 -05:00
|
|
|
if (GetSize(sig) == 0)
|
2014-07-27 09:19:24 -05:00
|
|
|
continue;
|
|
|
|
|
2014-08-03 05:40:43 -05:00
|
|
|
for (auto &tpl_name : celltypeMap.at(cell_type)) {
|
2014-07-27 09:19:24 -05:00
|
|
|
RTLIL::Module *tpl = map->modules_[tpl_name];
|
|
|
|
RTLIL::Wire *port = tpl->wire(conn.first);
|
|
|
|
if (port && port->port_input)
|
|
|
|
cell_to_inbit[cell].insert(sig.begin(), sig.end());
|
|
|
|
if (port && port->port_output)
|
|
|
|
for (auto &bit : sig)
|
|
|
|
outbit_to_cell[bit].insert(cell);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
cells.node(cell);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (auto &it_right : cell_to_inbit)
|
|
|
|
for (auto &it_sigbit : it_right.second)
|
|
|
|
for (auto &it_left : outbit_to_cell[it_sigbit])
|
|
|
|
cells.edge(it_left, it_right.first);
|
|
|
|
|
|
|
|
cells.sort();
|
|
|
|
|
|
|
|
for (auto cell : cells.sorted)
|
|
|
|
{
|
|
|
|
log_assert(handled_cells.count(cell) == 0);
|
|
|
|
log_assert(cell == module->cell(cell->name));
|
2014-07-30 19:21:41 -05:00
|
|
|
bool mapped_cell = false;
|
2014-07-27 09:19:24 -05:00
|
|
|
|
2014-08-03 05:40:43 -05:00
|
|
|
std::string cell_type = cell->type.str();
|
2017-08-29 15:46:35 -05:00
|
|
|
|
2019-08-07 14:20:08 -05:00
|
|
|
if (in_recursion && cell->type.begins_with("\\$"))
|
2014-08-03 05:40:43 -05:00
|
|
|
cell_type = cell_type.substr(1);
|
|
|
|
|
|
|
|
for (auto &tpl_name : celltypeMap.at(cell_type))
|
2014-02-16 10:16:44 -06:00
|
|
|
{
|
2014-08-02 06:11:01 -05:00
|
|
|
RTLIL::IdString derived_name = tpl_name;
|
2014-07-27 03:18:00 -05:00
|
|
|
RTLIL::Module *tpl = map->modules_[tpl_name];
|
2014-12-26 03:53:21 -06:00
|
|
|
std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2019-04-18 12:19:45 -05:00
|
|
|
if (tpl->get_blackbox_attribute(ignore_wb))
|
2014-07-17 01:58:51 -05:00
|
|
|
continue;
|
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
if (!flatten_mode)
|
|
|
|
{
|
2014-09-07 11:23:37 -05:00
|
|
|
std::string extmapper_name;
|
|
|
|
|
2019-08-15 12:25:54 -05:00
|
|
|
if (tpl->get_bool_attribute(ID(techmap_simplemap)))
|
2014-09-07 11:23:37 -05:00
|
|
|
extmapper_name = "simplemap";
|
|
|
|
|
2019-08-15 12:25:54 -05:00
|
|
|
if (tpl->get_bool_attribute(ID(techmap_maccmap)))
|
2014-09-07 11:23:37 -05:00
|
|
|
extmapper_name = "maccmap";
|
|
|
|
|
2019-08-15 12:25:54 -05:00
|
|
|
if (tpl->attributes.count(ID(techmap_wrap)))
|
2014-09-14 07:49:26 -05:00
|
|
|
extmapper_name = "wrap";
|
|
|
|
|
2014-09-07 11:23:37 -05:00
|
|
|
if (!extmapper_name.empty())
|
2014-07-27 14:13:23 -05:00
|
|
|
{
|
2014-08-03 05:40:43 -05:00
|
|
|
cell->type = cell_type;
|
|
|
|
|
2014-09-14 07:49:26 -05:00
|
|
|
if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
|
2014-07-27 14:13:23 -05:00
|
|
|
{
|
2014-09-07 11:23:37 -05:00
|
|
|
std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
|
2014-08-02 14:55:13 -05:00
|
|
|
|
|
|
|
for (auto &c : cell->parameters)
|
|
|
|
m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
|
|
|
|
|
2014-09-14 08:34:36 -05:00
|
|
|
if (extmapper_name == "wrap")
|
2019-08-15 12:25:54 -05:00
|
|
|
m_name += ":" + sha1(tpl->attributes.at(ID(techmap_wrap)).decode_string());
|
2014-09-14 08:34:36 -05:00
|
|
|
|
2014-09-14 07:49:26 -05:00
|
|
|
RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
|
|
|
|
RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
|
2014-08-02 14:55:13 -05:00
|
|
|
|
2014-09-07 11:23:37 -05:00
|
|
|
if (extmapper_module == nullptr)
|
2014-08-02 14:55:13 -05:00
|
|
|
{
|
2014-09-14 07:49:26 -05:00
|
|
|
extmapper_module = extmapper_design->addModule(m_name);
|
2014-09-07 11:23:37 -05:00
|
|
|
RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
|
2014-08-02 14:55:13 -05:00
|
|
|
|
2017-08-31 15:51:56 -05:00
|
|
|
extmapper_cell->set_src_attribute(cell->get_src_attribute());
|
2017-08-29 15:46:35 -05:00
|
|
|
|
2014-08-02 14:55:13 -05:00
|
|
|
int port_counter = 1;
|
2014-09-07 11:23:37 -05:00
|
|
|
for (auto &c : extmapper_cell->connections_) {
|
2014-10-10 09:59:44 -05:00
|
|
|
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
|
2019-08-15 16:50:10 -05:00
|
|
|
if (w->name.in(ID::Y, ID(Q)))
|
2014-08-02 14:55:13 -05:00
|
|
|
w->port_output = true;
|
|
|
|
else
|
|
|
|
w->port_input = true;
|
|
|
|
w->port_id = port_counter++;
|
|
|
|
c.second = w;
|
|
|
|
}
|
|
|
|
|
2014-09-14 07:49:26 -05:00
|
|
|
extmapper_module->fixup_ports();
|
2014-09-07 11:23:37 -05:00
|
|
|
extmapper_module->check();
|
|
|
|
|
|
|
|
if (extmapper_name == "simplemap") {
|
|
|
|
log("Creating %s with simplemap.\n", log_id(extmapper_module));
|
|
|
|
if (simplemap_mappers.count(extmapper_cell->type) == 0)
|
|
|
|
log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
|
|
|
|
simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
|
2014-09-14 07:49:26 -05:00
|
|
|
extmapper_module->remove(extmapper_cell);
|
2014-09-07 11:23:37 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
if (extmapper_name == "maccmap") {
|
|
|
|
log("Creating %s with maccmap.\n", log_id(extmapper_module));
|
2019-08-15 12:05:08 -05:00
|
|
|
if (extmapper_cell->type != ID($macc))
|
2014-09-07 11:23:37 -05:00
|
|
|
log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
|
|
|
|
maccmap(extmapper_module, extmapper_cell);
|
2014-09-14 07:49:26 -05:00
|
|
|
extmapper_module->remove(extmapper_cell);
|
2014-09-07 11:23:37 -05:00
|
|
|
}
|
2014-08-02 14:55:13 -05:00
|
|
|
|
2014-09-14 07:49:26 -05:00
|
|
|
if (extmapper_name == "wrap") {
|
2019-08-15 12:25:54 -05:00
|
|
|
std::string cmd_string = tpl->attributes.at(ID(techmap_wrap)).decode_string();
|
2014-09-14 07:49:26 -05:00
|
|
|
log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
|
2019-04-22 10:25:52 -05:00
|
|
|
mkdebug.on();
|
2014-09-14 07:49:26 -05:00
|
|
|
Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
|
|
|
|
log_continue = true;
|
|
|
|
}
|
2014-08-02 14:55:13 -05:00
|
|
|
}
|
|
|
|
|
2014-09-07 11:23:37 -05:00
|
|
|
cell->type = extmapper_module->name;
|
2014-08-02 14:55:13 -05:00
|
|
|
cell->parameters.clear();
|
2014-09-14 07:49:26 -05:00
|
|
|
|
|
|
|
if (!extern_mode || in_recursion) {
|
|
|
|
tpl = extmapper_module;
|
|
|
|
goto use_wrapper_tpl;
|
|
|
|
}
|
|
|
|
|
2019-04-22 10:25:52 -05:00
|
|
|
auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
|
|
|
|
if (!log_msg_cache.count(msg)) {
|
|
|
|
log_msg_cache.insert(msg);
|
|
|
|
log("%s\n", msg.c_str());
|
|
|
|
}
|
|
|
|
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
|
2014-07-27 14:13:23 -05:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-04-22 10:25:52 -05:00
|
|
|
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
|
|
|
|
if (!log_msg_cache.count(msg)) {
|
|
|
|
log_msg_cache.insert(msg);
|
|
|
|
log("%s\n", msg.c_str());
|
|
|
|
}
|
|
|
|
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
|
2014-09-07 11:23:37 -05:00
|
|
|
|
|
|
|
if (extmapper_name == "simplemap") {
|
|
|
|
if (simplemap_mappers.count(cell->type) == 0)
|
|
|
|
log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
|
|
|
|
simplemap_mappers.at(cell->type)(module, cell);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (extmapper_name == "maccmap") {
|
2019-08-15 12:05:08 -05:00
|
|
|
if (cell->type != ID($macc))
|
2014-09-07 11:23:37 -05:00
|
|
|
log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
|
|
|
|
maccmap(module, cell);
|
|
|
|
}
|
|
|
|
|
2014-07-27 14:13:23 -05:00
|
|
|
module->remove(cell);
|
|
|
|
cell = NULL;
|
|
|
|
}
|
2014-08-02 14:55:13 -05:00
|
|
|
|
|
|
|
did_something = true;
|
|
|
|
mapped_cell = true;
|
|
|
|
break;
|
2014-02-16 10:16:44 -06:00
|
|
|
}
|
2013-04-27 11:30:29 -05:00
|
|
|
|
2014-07-26 07:32:50 -05:00
|
|
|
for (auto conn : cell->connections()) {
|
2019-08-07 14:20:08 -05:00
|
|
|
if (conn.first.begins_with("$"))
|
2014-02-16 10:16:44 -06:00
|
|
|
continue;
|
2014-07-26 18:49:51 -05:00
|
|
|
if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
|
2014-02-16 10:16:44 -06:00
|
|
|
continue;
|
|
|
|
if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
|
|
|
|
goto next_tpl;
|
|
|
|
parameters[conn.first] = conn.second.as_const();
|
|
|
|
}
|
2013-11-24 16:31:14 -06:00
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
if (0) {
|
|
|
|
next_tpl:
|
2013-11-23 08:58:06 -06:00
|
|
|
continue;
|
2014-02-16 10:16:44 -06:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2019-08-15 12:25:54 -05:00
|
|
|
if (tpl->avail_parameters.count(ID(_TECHMAP_CELLTYPE_)) != 0)
|
|
|
|
parameters[ID(_TECHMAP_CELLTYPE_)] = RTLIL::unescape_id(cell->type);
|
2014-02-16 14:58:59 -06:00
|
|
|
|
2014-07-26 07:32:50 -05:00
|
|
|
for (auto conn : cell->connections()) {
|
2014-02-16 14:58:59 -06:00
|
|
|
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
|
|
|
|
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
|
|
|
|
for (auto &bit : v)
|
|
|
|
bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
|
|
|
|
parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
|
|
|
|
}
|
|
|
|
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
|
|
|
|
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
|
|
|
|
for (auto &bit : v)
|
|
|
|
if (bit.wire != NULL)
|
|
|
|
bit = RTLIL::SigBit(RTLIL::State::Sx);
|
|
|
|
parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
|
|
|
|
}
|
2019-08-15 22:14:03 -05:00
|
|
|
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))) != 0) {
|
|
|
|
auto sig = sigmap(conn.second);
|
|
|
|
RTLIL::Const value(State::Sx, sig.size());
|
|
|
|
for (int i = 0; i < sig.size(); i++) {
|
|
|
|
auto it = init_bits.find(sig[i]);
|
|
|
|
if (it != init_bits.end()) {
|
|
|
|
value[i] = it->second;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
parameters[stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))] = value;
|
|
|
|
}
|
2014-02-16 14:58:59 -06:00
|
|
|
}
|
2014-02-18 12:23:32 -06:00
|
|
|
|
|
|
|
int unique_bit_id_counter = 0;
|
|
|
|
std::map<RTLIL::SigBit, int> unique_bit_id;
|
|
|
|
unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
|
|
|
|
unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
|
|
|
|
unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
|
|
|
|
unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
|
|
|
|
|
2014-07-26 07:32:50 -05:00
|
|
|
for (auto conn : cell->connections())
|
2014-02-18 12:23:32 -06:00
|
|
|
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
|
|
|
|
for (auto &bit : sigmap(conn.second).to_sigbit_vector())
|
|
|
|
if (unique_bit_id.count(bit) == 0)
|
|
|
|
unique_bit_id[bit] = unique_bit_id_counter++;
|
|
|
|
}
|
|
|
|
|
2019-07-09 14:14:00 -05:00
|
|
|
// Find highest bit set
|
2014-02-18 12:23:32 -06:00
|
|
|
int bits = 0;
|
|
|
|
for (int i = 0; i < 32; i++)
|
|
|
|
if (((unique_bit_id_counter-1) & (1 << i)) != 0)
|
|
|
|
bits = i;
|
2019-07-09 14:14:00 -05:00
|
|
|
// Increment index by one to get number of bits
|
|
|
|
bits++;
|
2019-08-15 12:25:54 -05:00
|
|
|
if (tpl->avail_parameters.count(ID(_TECHMAP_BITS_CONNMAP_)))
|
|
|
|
parameters[ID(_TECHMAP_BITS_CONNMAP_)] = bits;
|
2014-02-18 12:23:32 -06:00
|
|
|
|
2014-07-26 07:32:50 -05:00
|
|
|
for (auto conn : cell->connections())
|
2014-02-18 12:23:32 -06:00
|
|
|
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
|
|
|
|
RTLIL::Const value;
|
|
|
|
for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
|
|
|
|
RTLIL::Const chunk(unique_bit_id.at(bit), bits);
|
|
|
|
value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
|
|
|
|
}
|
|
|
|
parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
|
|
|
|
}
|
2013-11-23 08:58:06 -06:00
|
|
|
}
|
2013-11-24 13:29:07 -06:00
|
|
|
|
2014-09-14 08:34:36 -05:00
|
|
|
if (0) {
|
|
|
|
use_wrapper_tpl:;
|
|
|
|
// do not register techmap_wrap modules with techmap_cache
|
2014-02-16 10:16:44 -06:00
|
|
|
} else {
|
2014-09-14 08:34:36 -05:00
|
|
|
std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
|
|
|
|
if (techmap_cache.count(key) > 0) {
|
|
|
|
tpl = techmap_cache[key];
|
|
|
|
} else {
|
2016-09-14 13:46:54 -05:00
|
|
|
if (parameters.size() != 0) {
|
2019-04-22 10:25:52 -05:00
|
|
|
mkdebug.on();
|
2014-12-26 03:53:21 -06:00
|
|
|
derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end()));
|
2014-09-14 08:34:36 -05:00
|
|
|
tpl = map->module(derived_name);
|
|
|
|
log_continue = true;
|
|
|
|
}
|
|
|
|
techmap_cache[key] = tpl;
|
2014-02-16 10:16:44 -06:00
|
|
|
}
|
2013-03-28 04:12:50 -05:00
|
|
|
}
|
2013-11-23 08:58:06 -06:00
|
|
|
|
2014-07-30 15:04:30 -05:00
|
|
|
if (flatten_mode) {
|
2014-02-16 10:16:44 -06:00
|
|
|
techmap_do_cache[tpl] = true;
|
2014-07-30 15:04:30 -05:00
|
|
|
} else {
|
|
|
|
RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
|
|
|
|
if (constmapped_tpl != nullptr)
|
|
|
|
tpl = constmapped_tpl;
|
|
|
|
}
|
2013-11-23 08:58:06 -06:00
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
if (techmap_do_cache.count(tpl) == 0)
|
2013-11-23 08:58:06 -06:00
|
|
|
{
|
2014-02-16 10:16:44 -06:00
|
|
|
bool keep_running = true;
|
|
|
|
techmap_do_cache[tpl] = true;
|
|
|
|
|
2014-02-16 15:18:06 -06:00
|
|
|
std::set<std::string> techmap_wire_names;
|
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
while (keep_running)
|
|
|
|
{
|
|
|
|
TechmapWires twd = techmap_find_special_wires(tpl);
|
|
|
|
keep_running = false;
|
|
|
|
|
2014-02-16 15:18:06 -06:00
|
|
|
for (auto &it : twd)
|
|
|
|
techmap_wire_names.insert(it.first);
|
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
for (auto &it : twd["_TECHMAP_FAIL_"]) {
|
|
|
|
RTLIL::SigSpec value = it.value;
|
|
|
|
if (value.is_fully_const() && value.as_bool()) {
|
|
|
|
log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
|
|
|
|
derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
|
|
|
|
techmap_do_cache[tpl] = false;
|
|
|
|
}
|
2013-11-23 08:58:06 -06:00
|
|
|
}
|
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
if (!techmap_do_cache[tpl])
|
|
|
|
break;
|
2013-11-23 08:58:06 -06:00
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
for (auto &it : twd)
|
|
|
|
{
|
2019-08-07 14:20:08 -05:00
|
|
|
if (it.first.compare(0, 12, "_TECHMAP_DO_") != 0 || it.second.empty())
|
2014-02-16 10:16:44 -06:00
|
|
|
continue;
|
2013-11-23 08:58:06 -06:00
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
auto &data = it.second.front();
|
2013-11-23 08:58:06 -06:00
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
if (!data.value.is_fully_const())
|
|
|
|
log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
|
2013-11-23 08:58:06 -06:00
|
|
|
|
2014-02-16 15:18:06 -06:00
|
|
|
techmap_wire_names.erase(it.first);
|
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
const char *p = data.wire->name.c_str();
|
|
|
|
const char *q = strrchr(p+1, '.');
|
|
|
|
q = q ? q : p+1;
|
2013-11-23 08:58:06 -06:00
|
|
|
|
2014-07-30 15:04:30 -05:00
|
|
|
std::string cmd_string = data.value.as_const().decode_string();
|
|
|
|
|
2014-08-03 05:40:43 -05:00
|
|
|
restart_eval_cmd_string:
|
2014-07-30 15:04:30 -05:00
|
|
|
if (cmd_string.rfind("CONSTMAP; ", 0) == 0)
|
|
|
|
{
|
|
|
|
cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
|
|
|
|
|
|
|
|
log("Analyzing pattern of constant bits for this cell:\n");
|
2014-08-02 09:03:18 -05:00
|
|
|
RTLIL::IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
|
2014-07-30 15:04:30 -05:00
|
|
|
log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
|
|
|
|
log_assert(map->module(new_tpl_name) == nullptr);
|
|
|
|
|
|
|
|
RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
|
|
|
|
tpl->cloneInto(new_tpl);
|
|
|
|
|
|
|
|
techmap_do_cache.erase(tpl);
|
|
|
|
techmap_do_cache[new_tpl] = true;
|
|
|
|
tpl = new_tpl;
|
|
|
|
|
|
|
|
std::map<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
|
|
|
|
std::map<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
|
|
|
|
std::map<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
|
|
|
|
|
|
|
|
for (auto wire : tpl->wires().to_vector())
|
|
|
|
{
|
|
|
|
if (!wire->port_input || wire->port_output)
|
|
|
|
continue;
|
|
|
|
|
2014-08-02 06:11:01 -05:00
|
|
|
RTLIL::IdString port_name = wire->name;
|
2014-07-30 15:04:30 -05:00
|
|
|
tpl->rename(wire, NEW_ID);
|
|
|
|
|
|
|
|
RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
|
|
|
|
wire->port_input = false;
|
2014-08-02 13:54:30 -05:00
|
|
|
wire->port_id = 0;
|
2014-07-30 15:04:30 -05:00
|
|
|
|
|
|
|
for (int i = 0; i < wire->width; i++) {
|
|
|
|
port_new2old_map[RTLIL::SigBit(new_wire, i)] = RTLIL::SigBit(wire, i);
|
|
|
|
port_connmap[RTLIL::SigBit(wire, i)] = RTLIL::SigBit(new_wire, i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (auto conn : cell->connections())
|
2014-10-10 09:59:44 -05:00
|
|
|
for (int i = 0; i < GetSize(conn.second); i++)
|
2014-07-30 15:04:30 -05:00
|
|
|
{
|
|
|
|
RTLIL::SigBit bit = sigmap(conn.second[i]);
|
|
|
|
RTLIL::SigBit tplbit(tpl->wire(conn.first), i);
|
|
|
|
|
|
|
|
if (bit.wire == nullptr)
|
|
|
|
{
|
|
|
|
RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
|
|
|
|
port_connmap.at(oldbit) = bit;
|
|
|
|
}
|
|
|
|
else if (cellbits_to_tplbits.count(bit))
|
|
|
|
{
|
|
|
|
RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
|
|
|
|
port_connmap.at(oldbit) = cellbits_to_tplbits[bit];
|
|
|
|
}
|
|
|
|
else
|
|
|
|
cellbits_to_tplbits[bit] = tplbit;
|
|
|
|
}
|
|
|
|
|
|
|
|
RTLIL::SigSig port_conn;
|
|
|
|
for (auto &it : port_connmap) {
|
|
|
|
port_conn.first.append_bit(it.first);
|
|
|
|
port_conn.second.append_bit(it.second);
|
|
|
|
}
|
|
|
|
tpl->connect(port_conn);
|
2014-08-02 14:55:13 -05:00
|
|
|
|
|
|
|
tpl->check();
|
2014-08-03 05:40:43 -05:00
|
|
|
goto restart_eval_cmd_string;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cmd_string.rfind("RECURSION; ", 0) == 0)
|
|
|
|
{
|
|
|
|
cmd_string = cmd_string.substr(strlen("RECURSION; "));
|
|
|
|
while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
|
|
|
|
goto restart_eval_cmd_string;
|
2014-07-30 15:04:30 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
Pass::call_on_module(map, tpl, cmd_string);
|
|
|
|
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
|
2014-02-16 10:16:44 -06:00
|
|
|
std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
|
2014-07-26 18:49:51 -05:00
|
|
|
while (tpl->wires_.count(new_name))
|
2014-02-16 10:16:44 -06:00
|
|
|
new_name += "_";
|
2014-07-30 15:04:30 -05:00
|
|
|
tpl->rename(data.wire->name, new_name);
|
2013-11-23 08:58:06 -06:00
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
keep_running = true;
|
|
|
|
break;
|
|
|
|
}
|
2013-11-23 08:58:06 -06:00
|
|
|
}
|
2013-03-28 04:12:50 -05:00
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
TechmapWires twd = techmap_find_special_wires(tpl);
|
|
|
|
for (auto &it : twd) {
|
2019-08-15 22:14:03 -05:00
|
|
|
if (it.first != "_TECHMAP_FAIL_" && (it.first.substr(0, 20) != "_TECHMAP_REMOVEINIT_" || it.first[it.first.size()-1] != '_') && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
|
2014-02-16 10:16:44 -06:00
|
|
|
log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
|
|
|
|
if (techmap_do_cache[tpl])
|
|
|
|
for (auto &it2 : it.second)
|
|
|
|
if (!it2.value.is_fully_const())
|
|
|
|
log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
|
2014-02-16 15:18:06 -06:00
|
|
|
techmap_wire_names.erase(it.first);
|
2014-02-16 10:16:44 -06:00
|
|
|
}
|
2014-02-16 15:18:06 -06:00
|
|
|
|
|
|
|
for (auto &it : techmap_wire_names)
|
|
|
|
log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
|
2014-08-03 05:40:43 -05:00
|
|
|
|
|
|
|
if (recursive_mode) {
|
|
|
|
if (log_continue) {
|
2016-04-21 16:28:37 -05:00
|
|
|
log_header(design, "Continuing TECHMAP pass.\n");
|
2014-08-03 05:40:43 -05:00
|
|
|
log_continue = false;
|
2019-04-22 10:25:52 -05:00
|
|
|
mkdebug.off();
|
2014-08-03 05:40:43 -05:00
|
|
|
}
|
|
|
|
while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
|
|
|
|
}
|
2013-11-23 08:58:06 -06:00
|
|
|
}
|
2013-08-09 08:20:22 -05:00
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
if (techmap_do_cache.at(tpl) == false)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (log_continue) {
|
2016-04-21 16:28:37 -05:00
|
|
|
log_header(design, "Continuing TECHMAP pass.\n");
|
2014-02-16 10:16:44 -06:00
|
|
|
log_continue = false;
|
2019-04-22 10:25:52 -05:00
|
|
|
mkdebug.off();
|
2014-02-16 10:16:44 -06:00
|
|
|
}
|
2013-11-23 08:58:06 -06:00
|
|
|
|
2019-09-27 04:03:04 -05:00
|
|
|
TechmapWires twd = techmap_find_special_wires(tpl);
|
|
|
|
for (auto &it : twd) {
|
|
|
|
if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_") {
|
|
|
|
for (auto &it2 : it.second) {
|
|
|
|
auto val = it2.value.as_const();
|
|
|
|
auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1));
|
|
|
|
auto it = cell->connections().find(wirename);
|
|
|
|
if (it != cell->connections().end()) {
|
|
|
|
auto sig = sigmap(it->second);
|
|
|
|
for (int i = 0; i < sig.size(); i++)
|
|
|
|
if (val[i] == State::S1)
|
|
|
|
remove_init_bits.insert(sig[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-08-03 05:40:43 -05:00
|
|
|
if (extern_mode && !in_recursion)
|
2014-07-27 14:13:23 -05:00
|
|
|
{
|
|
|
|
std::string m_name = stringf("$extern:%s", log_id(tpl));
|
|
|
|
|
|
|
|
if (!design->module(m_name))
|
|
|
|
{
|
|
|
|
RTLIL::Module *m = design->addModule(m_name);
|
|
|
|
tpl->cloneInto(m);
|
|
|
|
|
|
|
|
for (auto cell : m->cells()) {
|
2019-08-07 14:20:08 -05:00
|
|
|
if (cell->type.begins_with("\\$"))
|
2014-07-27 14:13:23 -05:00
|
|
|
cell->type = cell->type.substr(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_queue.insert(m);
|
|
|
|
}
|
|
|
|
|
2019-04-22 10:25:52 -05:00
|
|
|
log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
|
2014-07-27 14:13:23 -05:00
|
|
|
cell->type = m_name;
|
|
|
|
cell->parameters.clear();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-04-22 10:25:52 -05:00
|
|
|
auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
|
|
|
|
if (!log_msg_cache.count(msg)) {
|
|
|
|
log_msg_cache.insert(msg);
|
|
|
|
log("%s\n", msg.c_str());
|
|
|
|
}
|
|
|
|
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
|
2014-07-30 19:21:41 -05:00
|
|
|
techmap_module_worker(design, module, cell, tpl);
|
2014-07-27 14:13:23 -05:00
|
|
|
cell = NULL;
|
|
|
|
}
|
2014-02-16 10:16:44 -06:00
|
|
|
did_something = true;
|
2014-07-30 19:21:41 -05:00
|
|
|
mapped_cell = true;
|
2014-02-16 10:16:44 -06:00
|
|
|
break;
|
2013-11-23 08:58:06 -06:00
|
|
|
}
|
|
|
|
|
2014-07-30 19:21:41 -05:00
|
|
|
if (assert_mode && !mapped_cell)
|
|
|
|
log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
|
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
handled_cells.insert(cell);
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2019-08-15 22:14:03 -05:00
|
|
|
if (!remove_init_bits.empty()) {
|
|
|
|
for (auto wire : module->wires())
|
|
|
|
if (wire->attributes.count("\\init")) {
|
|
|
|
Const &value = wire->attributes.at("\\init");
|
|
|
|
bool do_cleanup = true;
|
|
|
|
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
|
|
|
|
SigBit bit = sigmap(SigBit(wire, i));
|
|
|
|
if (remove_init_bits.count(bit))
|
|
|
|
value[i] = State::Sx;
|
|
|
|
else if (value[i] != State::Sx)
|
|
|
|
do_cleanup = false;
|
|
|
|
}
|
|
|
|
if (do_cleanup) {
|
|
|
|
log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
|
|
|
|
wire->attributes.erase("\\init");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
if (log_continue) {
|
2016-04-21 16:28:37 -05:00
|
|
|
log_header(design, "Continuing TECHMAP pass.\n");
|
2014-02-16 10:16:44 -06:00
|
|
|
log_continue = false;
|
2019-04-22 10:25:52 -05:00
|
|
|
mkdebug.off();
|
2014-02-16 10:16:44 -06:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
return did_something;
|
2013-08-09 08:20:22 -05:00
|
|
|
}
|
2014-02-16 10:16:44 -06:00
|
|
|
};
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
struct TechmapPass : public Pass {
|
2014-02-06 06:10:06 -06:00
|
|
|
TechmapPass() : Pass("techmap", "generic technology mapper") { }
|
2018-07-21 01:41:18 -05:00
|
|
|
void help() YS_OVERRIDE
|
2013-02-28 17:36:19 -06:00
|
|
|
{
|
|
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
|
|
log("\n");
|
|
|
|
log(" techmap [-map filename] [selection]\n");
|
|
|
|
log("\n");
|
2013-03-17 16:02:30 -05:00
|
|
|
log("This pass implements a very simple technology mapper that replaces cells in\n");
|
2015-08-14 03:56:05 -05:00
|
|
|
log("the design with implementations given in form of a Verilog or ilang source\n");
|
2013-02-28 17:36:19 -06:00
|
|
|
log("file.\n");
|
|
|
|
log("\n");
|
|
|
|
log(" -map filename\n");
|
|
|
|
log(" the library of cell implementations to be used.\n");
|
|
|
|
log(" without this parameter a builtin library is used that\n");
|
2013-03-17 16:02:30 -05:00
|
|
|
log(" transforms the internal RTL cells to the internal gate\n");
|
2013-02-28 17:36:19 -06:00
|
|
|
log(" library.\n");
|
|
|
|
log("\n");
|
2014-08-14 19:00:53 -05:00
|
|
|
log(" -map %%<design-name>\n");
|
|
|
|
log(" like -map above, but with an in-memory design instead of a file.\n");
|
|
|
|
log("\n");
|
2014-07-27 14:13:23 -05:00
|
|
|
log(" -extern\n");
|
|
|
|
log(" load the cell implementations as separate modules into the design\n");
|
|
|
|
log(" instead of inlining them.\n");
|
|
|
|
log("\n");
|
2014-03-06 05:15:17 -06:00
|
|
|
log(" -max_iter <number>\n");
|
2019-08-20 22:05:51 -05:00
|
|
|
log(" only run the specified number of iterations on each module.\n");
|
2019-08-20 21:48:16 -05:00
|
|
|
log(" default: unlimited\n");
|
2014-03-06 05:15:17 -06:00
|
|
|
log("\n");
|
2014-08-03 05:40:43 -05:00
|
|
|
log(" -recursive\n");
|
|
|
|
log(" instead of the iterative breadth-first algorithm use a recursive\n");
|
2015-08-14 03:56:05 -05:00
|
|
|
log(" depth-first algorithm. both methods should yield equivalent results,\n");
|
2014-08-03 05:40:43 -05:00
|
|
|
log(" but may differ in performance.\n");
|
|
|
|
log("\n");
|
2014-09-01 08:36:29 -05:00
|
|
|
log(" -autoproc\n");
|
|
|
|
log(" Automatically call \"proc\" on implementations that contain processes.\n");
|
|
|
|
log("\n");
|
2019-04-20 04:23:24 -05:00
|
|
|
log(" -wb\n");
|
|
|
|
log(" Ignore the 'whitebox' attribute on cell implementations.\n");
|
|
|
|
log("\n");
|
2014-07-30 19:21:41 -05:00
|
|
|
log(" -assert\n");
|
|
|
|
log(" this option will cause techmap to exit with an error if it can't map\n");
|
|
|
|
log(" a selected cell. only cell types that end on an underscore are accepted\n");
|
|
|
|
log(" as final cell types by this mode.\n");
|
|
|
|
log("\n");
|
2013-11-24 13:04:48 -06:00
|
|
|
log(" -D <define>, -I <incdir>\n");
|
2015-08-14 03:56:05 -05:00
|
|
|
log(" this options are passed as-is to the Verilog frontend for loading the\n");
|
|
|
|
log(" map file. Note that the Verilog frontend is also called with the\n");
|
2018-05-03 08:25:59 -05:00
|
|
|
log(" '-nooverwrite' option set.\n");
|
2013-11-24 13:04:48 -06:00
|
|
|
log("\n");
|
2013-11-23 08:58:06 -06:00
|
|
|
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
|
2013-11-24 16:31:14 -06:00
|
|
|
log("match cells with a type that match the text value of this attribute. Otherwise\n");
|
|
|
|
log("the module name will be used to match the cell.\n");
|
|
|
|
log("\n");
|
|
|
|
log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
|
|
|
|
log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
|
2013-08-09 08:20:22 -05:00
|
|
|
log("\n");
|
2014-09-07 11:23:37 -05:00
|
|
|
log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
|
|
|
|
log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
|
|
|
|
log("\n");
|
2014-09-14 07:49:26 -05:00
|
|
|
log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
|
|
|
|
log("will create a wrapper for the cell and then run the command string that the\n");
|
|
|
|
log("attribute is set to on the wrapper module.\n");
|
|
|
|
log("\n");
|
2019-09-19 12:26:09 -05:00
|
|
|
log("When a port on a module in the map file has the 'techmap_autopurge' attribute\n");
|
|
|
|
log("set, and that port is not connected in the instantiation that is mapped, then\n");
|
|
|
|
log("then a cell port connected only to such wires will be omitted in the mapped\n");
|
|
|
|
log("version of the circuit.\n");
|
|
|
|
log("\n");
|
2013-11-23 08:58:06 -06:00
|
|
|
log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
|
|
|
|
log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
|
2013-11-24 16:31:14 -06:00
|
|
|
log("the mapping module to the techmap command. At the moment the following special\n");
|
2013-11-23 08:58:06 -06:00
|
|
|
log("wires are supported:\n");
|
2013-03-28 04:12:50 -05:00
|
|
|
log("\n");
|
2013-11-23 08:58:06 -06:00
|
|
|
log(" _TECHMAP_FAIL_\n");
|
|
|
|
log(" When this wire is set to a non-zero constant value, techmap will not\n");
|
|
|
|
log(" use this module and instead try the next module with a matching\n");
|
|
|
|
log(" 'techmap_celltype' attribute.\n");
|
|
|
|
log("\n");
|
|
|
|
log(" When such a wire exists but does not have a constant value after all\n");
|
|
|
|
log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
|
|
|
|
log("\n");
|
|
|
|
log(" _TECHMAP_DO_*\n");
|
|
|
|
log(" This wires are evaluated in alphabetical order. The constant text value\n");
|
|
|
|
log(" of this wire is a yosys command (or sequence of commands) that is run\n");
|
|
|
|
log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
|
|
|
|
log(" that are written using always-statements.\n");
|
|
|
|
log("\n");
|
|
|
|
log(" When such a wire has a non-constant value at the time it is to be\n");
|
|
|
|
log(" evaluated, an error is produced. That means it is possible for such a\n");
|
|
|
|
log(" wire to start out as non-constant and evaluate to a constant value\n");
|
|
|
|
log(" during processing of other _TECHMAP_DO_* commands.\n");
|
2013-04-27 11:30:29 -05:00
|
|
|
log("\n");
|
2014-07-30 15:04:30 -05:00
|
|
|
log(" A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n");
|
|
|
|
log(" in this case techmap will create a copy for each distinct configuration\n");
|
|
|
|
log(" of constant inputs and shorted inputs at this point and import the\n");
|
|
|
|
log(" constant and connected bits into the map module. All further commands\n");
|
|
|
|
log(" are executed in this copy. This is a very convenient way of creating\n");
|
2015-08-14 03:56:05 -05:00
|
|
|
log(" optimized specializations of techmap modules without using the special\n");
|
2014-07-30 15:04:30 -05:00
|
|
|
log(" parameters described below.\n");
|
|
|
|
log("\n");
|
2014-08-03 05:40:43 -05:00
|
|
|
log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
|
|
|
|
log(" then techmap will recursively replace the cells in the module with their\n");
|
|
|
|
log(" implementation. This is not affected by the -max_iter option.\n");
|
|
|
|
log("\n");
|
|
|
|
log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
|
|
|
|
log("\n");
|
2019-08-15 22:14:03 -05:00
|
|
|
log(" _TECHMAP_REMOVEINIT_<port-name>_\n");
|
|
|
|
log(" When this wire is set to a constant value, the init attribute of the wire(s)\n");
|
|
|
|
log(" connected to this port will be consumed. This wire must have the same\n");
|
|
|
|
log(" width as the given port, and for every bit that is set to 1 in the value,\n");
|
|
|
|
log(" the corresponding init attribute bit will be changed to 1'bx. If all\n");
|
|
|
|
log(" bits of an init attribute are left as x, it will be removed.\n");
|
|
|
|
log("\n");
|
2013-11-24 16:31:14 -06:00
|
|
|
log("In addition to this special wires, techmap also supports special parameters in\n");
|
|
|
|
log("modules in the map file:\n");
|
|
|
|
log("\n");
|
|
|
|
log(" _TECHMAP_CELLTYPE_\n");
|
|
|
|
log(" When a parameter with this name exists, it will be set to the type name\n");
|
|
|
|
log(" of the cell that matches the module.\n");
|
|
|
|
log("\n");
|
2014-02-16 14:58:59 -06:00
|
|
|
log(" _TECHMAP_CONSTMSK_<port-name>_\n");
|
|
|
|
log(" _TECHMAP_CONSTVAL_<port-name>_\n");
|
|
|
|
log(" When this pair of parameters is available in a module for a port, then\n");
|
|
|
|
log(" former has a 1-bit for each constant input bit and the latter has the\n");
|
|
|
|
log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
|
|
|
|
log("\n");
|
2019-08-15 22:14:03 -05:00
|
|
|
log(" _TECHMAP_WIREINIT_<port-name>_\n");
|
|
|
|
log(" When a parameter with this name exists, it will be set to the initial\n");
|
|
|
|
log(" value of the wire(s) connected to the given port, as specified by the init\n");
|
|
|
|
log(" attribute. If the attribute doesn't exist, x will be filled for the\n");
|
|
|
|
log(" missing bits. To remove the init attribute bits used, use the\n");
|
|
|
|
log(" _TECHMAP_REMOVEINIT_*_ wires.\n");
|
|
|
|
log("\n");
|
2014-02-18 12:23:32 -06:00
|
|
|
log(" _TECHMAP_BITS_CONNMAP_\n");
|
|
|
|
log(" _TECHMAP_CONNMAP_<port-name>_\n");
|
|
|
|
log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
|
|
|
|
log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
|
|
|
|
log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
|
|
|
|
log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
|
|
|
|
log(" This can be used to detect shorted inputs.\n");
|
|
|
|
log("\n");
|
2013-04-27 11:30:29 -05:00
|
|
|
log("When a module in the map file has a parameter where the according cell in the\n");
|
|
|
|
log("design has a port, the module from the map file is only used if the port in\n");
|
|
|
|
log("the design is connected to a constant value. The parameter is then set to the\n");
|
|
|
|
log("constant value.\n");
|
2013-03-28 04:12:50 -05:00
|
|
|
log("\n");
|
2014-02-20 16:42:07 -06:00
|
|
|
log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
|
2017-02-16 05:28:42 -06:00
|
|
|
log("and attributes of the cell that is being replaced.\n");
|
2019-10-02 14:43:35 -05:00
|
|
|
log("A cell with a name of the form `_TECHMAP_REPLACE_.<suffix>` in the map file will\n");
|
|
|
|
log("be named thus but with the `_TECHMAP_REPLACE_' prefix substituted with the name\n");
|
|
|
|
log("of the cell being replaced.\n");
|
|
|
|
log("Similarly, a wire named in the form `_TECHMAP_REPLACE_.<suffix>` will cause a\n");
|
|
|
|
log("new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'\n");
|
|
|
|
log("prefix also substituted.\n");
|
2014-02-20 16:42:07 -06:00
|
|
|
log("\n");
|
2013-02-28 17:36:19 -06:00
|
|
|
log("See 'help extract' for a pass that does the opposite thing.\n");
|
|
|
|
log("\n");
|
2013-04-27 11:30:29 -05:00
|
|
|
log("See 'help flatten' for a pass that does flatten the design (which is\n");
|
2015-08-14 03:56:05 -05:00
|
|
|
log("essentially techmap but using the design itself as map library).\n");
|
2013-04-27 11:30:29 -05:00
|
|
|
log("\n");
|
2013-02-28 17:36:19 -06:00
|
|
|
}
|
2018-07-21 01:41:18 -05:00
|
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2016-04-21 16:28:37 -05:00
|
|
|
log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
|
2013-01-05 04:13:26 -06:00
|
|
|
log_push();
|
|
|
|
|
2014-07-30 19:21:41 -05:00
|
|
|
TechmapWorker worker;
|
|
|
|
simplemap_get_mappers(worker.simplemap_mappers);
|
|
|
|
|
2013-11-23 08:58:06 -06:00
|
|
|
std::vector<std::string> map_files;
|
2019-04-21 19:07:36 -05:00
|
|
|
std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
|
2014-03-06 05:15:17 -06:00
|
|
|
int max_iter = -1;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
size_t argidx;
|
|
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
|
|
if (args[argidx] == "-map" && argidx+1 < args.size()) {
|
2015-04-08 05:14:34 -05:00
|
|
|
map_files.push_back(args[++argidx]);
|
2013-08-09 08:20:22 -05:00
|
|
|
continue;
|
|
|
|
}
|
2014-03-06 05:15:17 -06:00
|
|
|
if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
|
2019-08-07 13:09:17 -05:00
|
|
|
max_iter = atoi(args[++argidx].c_str());
|
2014-03-06 05:15:17 -06:00
|
|
|
continue;
|
|
|
|
}
|
2013-11-24 13:04:48 -06:00
|
|
|
if (args[argidx] == "-D" && argidx+1 < args.size()) {
|
|
|
|
verilog_frontend += " -D " + args[++argidx];
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (args[argidx] == "-I" && argidx+1 < args.size()) {
|
|
|
|
verilog_frontend += " -I " + args[++argidx];
|
|
|
|
continue;
|
|
|
|
}
|
2014-07-30 19:21:41 -05:00
|
|
|
if (args[argidx] == "-assert") {
|
|
|
|
worker.assert_mode = true;
|
|
|
|
continue;
|
|
|
|
}
|
2014-07-27 14:13:23 -05:00
|
|
|
if (args[argidx] == "-extern") {
|
2014-07-30 19:21:41 -05:00
|
|
|
worker.extern_mode = true;
|
2014-07-27 14:13:23 -05:00
|
|
|
continue;
|
|
|
|
}
|
2014-08-03 05:40:43 -05:00
|
|
|
if (args[argidx] == "-recursive") {
|
|
|
|
worker.recursive_mode = true;
|
|
|
|
continue;
|
|
|
|
}
|
2014-09-01 08:36:29 -05:00
|
|
|
if (args[argidx] == "-autoproc") {
|
|
|
|
worker.autoproc_mode = true;
|
|
|
|
continue;
|
|
|
|
}
|
2019-04-20 04:23:24 -05:00
|
|
|
if (args[argidx] == "-wb") {
|
|
|
|
worker.ignore_wb = true;
|
|
|
|
continue;
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
extra_args(args, argidx, design);
|
|
|
|
|
2013-02-28 17:36:19 -06:00
|
|
|
RTLIL::Design *map = new RTLIL::Design;
|
2013-11-23 08:58:06 -06:00
|
|
|
if (map_files.empty()) {
|
2014-08-23 08:03:55 -05:00
|
|
|
std::istringstream f(stdcells_code);
|
|
|
|
Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
|
2019-04-22 10:25:52 -05:00
|
|
|
} else {
|
2014-07-29 09:06:27 -05:00
|
|
|
for (auto &fn : map_files)
|
2019-08-07 14:20:08 -05:00
|
|
|
if (fn.compare(0, 1, "%") == 0) {
|
2014-07-29 09:06:27 -05:00
|
|
|
if (!saved_designs.count(fn.substr(1))) {
|
|
|
|
delete map;
|
|
|
|
log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1);
|
|
|
|
}
|
|
|
|
for (auto mod : saved_designs.at(fn.substr(1))->modules())
|
|
|
|
if (!map->has(mod->name))
|
|
|
|
map->add(mod->clone());
|
|
|
|
} else {
|
2014-08-23 08:03:55 -05:00
|
|
|
std::ifstream f;
|
2015-04-08 05:14:34 -05:00
|
|
|
rewrite_filename(fn);
|
2014-08-23 08:03:55 -05:00
|
|
|
f.open(fn.c_str());
|
2018-01-07 09:36:13 -06:00
|
|
|
yosys_input_files.insert(fn);
|
2014-08-23 08:03:55 -05:00
|
|
|
if (f.fail())
|
2014-07-29 09:06:27 -05:00
|
|
|
log_cmd_error("Can't open map file `%s'\n", fn.c_str());
|
2019-08-07 14:20:08 -05:00
|
|
|
Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
|
2014-07-29 09:06:27 -05:00
|
|
|
}
|
2019-04-22 10:25:52 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
log_header(design, "Continuing TECHMAP pass.\n");
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-08-14 19:40:46 -05:00
|
|
|
std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
|
2014-07-27 03:18:00 -05:00
|
|
|
for (auto &it : map->modules_) {
|
2019-08-15 12:25:54 -05:00
|
|
|
if (it.second->attributes.count(ID(techmap_celltype)) && !it.second->attributes.at(ID(techmap_celltype)).bits.empty()) {
|
|
|
|
char *p = strdup(it.second->attributes.at(ID(techmap_celltype)).decode_string().c_str());
|
2013-11-24 13:29:07 -06:00
|
|
|
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
|
|
|
|
celltypeMap[RTLIL::escape_id(q)].insert(it.first);
|
|
|
|
free(p);
|
2015-04-09 05:02:26 -05:00
|
|
|
} else {
|
|
|
|
string module_name = it.first.str();
|
2019-08-07 14:20:08 -05:00
|
|
|
if (it.first.begins_with("\\$"))
|
2015-04-09 05:02:26 -05:00
|
|
|
module_name = module_name.substr(1);
|
|
|
|
celltypeMap[module_name].insert(it.first);
|
|
|
|
}
|
2013-03-28 04:12:50 -05:00
|
|
|
}
|
|
|
|
|
2014-08-02 09:03:18 -05:00
|
|
|
for (auto module : design->modules())
|
|
|
|
worker.module_queue.insert(module);
|
|
|
|
|
2014-07-27 14:13:23 -05:00
|
|
|
while (!worker.module_queue.empty())
|
|
|
|
{
|
|
|
|
RTLIL::Module *module = *worker.module_queue.begin();
|
|
|
|
worker.module_queue.erase(module);
|
|
|
|
|
2019-08-20 21:48:16 -05:00
|
|
|
int module_max_iter = max_iter;
|
2014-07-27 09:19:24 -05:00
|
|
|
bool did_something = true;
|
|
|
|
std::set<RTLIL::Cell*> handled_cells;
|
|
|
|
while (did_something) {
|
|
|
|
did_something = false;
|
2019-08-20 21:48:16 -05:00
|
|
|
if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
|
|
|
|
did_something = true;
|
2014-07-27 09:19:24 -05:00
|
|
|
if (did_something)
|
|
|
|
module->check();
|
2019-08-20 21:48:16 -05:00
|
|
|
if (module_max_iter > 0 && --module_max_iter == 0)
|
2014-07-27 09:19:24 -05:00
|
|
|
break;
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
log("No more expansions possible.\n");
|
|
|
|
delete map;
|
2014-02-16 10:16:44 -06:00
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
log_pop();
|
|
|
|
}
|
|
|
|
} TechmapPass;
|
2015-07-02 04:14:30 -05:00
|
|
|
|
2013-04-26 07:40:45 -05:00
|
|
|
struct FlattenPass : public Pass {
|
|
|
|
FlattenPass() : Pass("flatten", "flatten design") { }
|
2018-07-21 01:41:18 -05:00
|
|
|
void help() YS_OVERRIDE
|
2013-04-26 07:40:45 -05:00
|
|
|
{
|
|
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
|
|
log("\n");
|
2019-04-18 12:19:45 -05:00
|
|
|
log(" flatten [options] [selection]\n");
|
2013-04-26 07:40:45 -05:00
|
|
|
log("\n");
|
|
|
|
log("This pass flattens the design by replacing cells by their implementation. This\n");
|
2015-08-14 03:56:05 -05:00
|
|
|
log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
|
2013-04-26 07:40:45 -05:00
|
|
|
log("pass is using the current design as mapping library.\n");
|
|
|
|
log("\n");
|
2015-08-14 15:23:01 -05:00
|
|
|
log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
|
2015-02-25 05:46:00 -06:00
|
|
|
log("flattened by this command.\n");
|
|
|
|
log("\n");
|
2019-04-18 12:19:45 -05:00
|
|
|
log(" -wb\n");
|
|
|
|
log(" Ignore the 'whitebox' attribute on cell implementations.\n");
|
|
|
|
log("\n");
|
2013-04-26 07:40:45 -05:00
|
|
|
}
|
2018-07-21 01:41:18 -05:00
|
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
2013-04-26 07:40:45 -05:00
|
|
|
{
|
2016-04-21 16:28:37 -05:00
|
|
|
log_header(design, "Executing FLATTEN pass (flatten design).\n");
|
2013-04-26 07:40:45 -05:00
|
|
|
log_push();
|
|
|
|
|
2014-02-16 10:16:44 -06:00
|
|
|
TechmapWorker worker;
|
2014-07-30 19:21:41 -05:00
|
|
|
worker.flatten_mode = true;
|
2014-02-16 10:16:44 -06:00
|
|
|
|
2019-04-18 12:19:45 -05:00
|
|
|
size_t argidx;
|
|
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
|
|
if (args[argidx] == "-wb") {
|
|
|
|
worker.ignore_wb = true;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
extra_args(args, argidx, design);
|
|
|
|
|
|
|
|
|
2014-08-14 19:40:46 -05:00
|
|
|
std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
|
2015-02-25 05:46:00 -06:00
|
|
|
for (auto module : design->modules())
|
|
|
|
celltypeMap[module->name].insert(module->name);
|
2013-04-26 07:40:45 -05:00
|
|
|
|
2013-11-23 22:03:43 -06:00
|
|
|
RTLIL::Module *top_mod = NULL;
|
2013-11-24 07:10:46 -06:00
|
|
|
if (design->full_selection())
|
2014-07-27 03:41:42 -05:00
|
|
|
for (auto mod : design->modules())
|
2019-08-15 12:25:54 -05:00
|
|
|
if (mod->get_bool_attribute(ID(top)))
|
2014-07-27 03:41:42 -05:00
|
|
|
top_mod = mod;
|
2013-11-23 22:03:43 -06:00
|
|
|
|
2013-04-26 07:40:45 -05:00
|
|
|
std::set<RTLIL::Cell*> handled_cells;
|
2015-02-25 05:46:00 -06:00
|
|
|
if (top_mod != NULL) {
|
|
|
|
worker.flatten_do_list.insert(top_mod->name);
|
|
|
|
while (!worker.flatten_do_list.empty()) {
|
|
|
|
auto mod = design->module(*worker.flatten_do_list.begin());
|
|
|
|
while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
|
|
|
|
worker.flatten_done_list.insert(mod->name);
|
|
|
|
worker.flatten_do_list.erase(mod->name);
|
2013-11-23 22:03:43 -06:00
|
|
|
}
|
2015-02-25 05:46:00 -06:00
|
|
|
} else {
|
2016-10-16 13:37:02 -05:00
|
|
|
for (auto mod : vector<Module*>(design->modules())) {
|
2015-02-25 05:46:00 -06:00
|
|
|
while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
|
2016-10-16 13:37:02 -05:00
|
|
|
}
|
2013-04-26 07:40:45 -05:00
|
|
|
}
|
|
|
|
|
2019-04-22 10:25:52 -05:00
|
|
|
log_suppressed();
|
2013-04-26 07:40:45 -05:00
|
|
|
log("No more expansions possible.\n");
|
2013-11-23 22:03:43 -06:00
|
|
|
|
2015-02-25 05:46:00 -06:00
|
|
|
if (top_mod != NULL)
|
|
|
|
{
|
|
|
|
pool<RTLIL::IdString> used_modules, new_used_modules;
|
|
|
|
new_used_modules.insert(top_mod->name);
|
|
|
|
while (!new_used_modules.empty()) {
|
|
|
|
pool<RTLIL::IdString> queue;
|
|
|
|
queue.swap(new_used_modules);
|
|
|
|
for (auto modname : queue)
|
|
|
|
used_modules.insert(modname);
|
|
|
|
for (auto modname : queue)
|
|
|
|
for (auto cell : design->module(modname)->cells())
|
|
|
|
if (design->module(cell->type) && !used_modules[cell->type])
|
|
|
|
new_used_modules.insert(cell->type);
|
|
|
|
}
|
|
|
|
|
2014-12-26 03:53:21 -06:00
|
|
|
dict<RTLIL::IdString, RTLIL::Module*> new_modules;
|
2015-02-21 08:01:13 -06:00
|
|
|
for (auto mod : vector<Module*>(design->modules()))
|
2019-04-18 12:19:45 -05:00
|
|
|
if (used_modules[mod->name] || mod->get_blackbox_attribute(worker.ignore_wb)) {
|
2014-07-27 03:41:42 -05:00
|
|
|
new_modules[mod->name] = mod;
|
2013-11-23 22:03:43 -06:00
|
|
|
} else {
|
2014-07-27 03:41:42 -05:00
|
|
|
log("Deleting now unused module %s.\n", log_id(mod));
|
|
|
|
delete mod;
|
2013-11-23 22:03:43 -06:00
|
|
|
}
|
2014-07-27 03:18:00 -05:00
|
|
|
design->modules_.swap(new_modules);
|
2013-11-23 22:03:43 -06:00
|
|
|
}
|
|
|
|
|
2013-04-26 07:40:45 -05:00
|
|
|
log_pop();
|
|
|
|
}
|
|
|
|
} FlattenPass;
|
2013-11-23 22:03:43 -06:00
|
|
|
|
2014-09-27 09:17:53 -05:00
|
|
|
PRIVATE_NAMESPACE_END
|