mirror of https://github.com/YosysHQ/yosys.git
9 lines
132 B
Systemverilog
9 lines
132 B
Systemverilog
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module top;
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rand const reg rx;
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const reg ry;
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rand reg rz;
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rand const integer ix;
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const integer iy;
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rand integer iz;
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endmodule
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