mirror of https://github.com/YosysHQ/yosys.git
29 lines
362 B
Systemverilog
29 lines
362 B
Systemverilog
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module top (
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input clk,
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input [5:0] currentstate,
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output reg [1:0] o
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);
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always @ (posedge clk)
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begin
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case (currentstate)
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5'd1,5'd2, 5'd3:
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begin
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o <= 2'b01;
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end
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5'd4:
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begin
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o <= 2'b10;
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end
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5'd5,5'd6,5'd7:
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begin
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o <= 2'b11;
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end
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default :
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begin
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o <= 2'b00;
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end
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endcase
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end
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endmodule
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