mirror of https://github.com/YosysHQ/yosys.git
89 lines
2.1 KiB
Systemverilog
89 lines
2.1 KiB
Systemverilog
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module top;
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typedef struct packed {
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logic a;
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logic signed b;
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byte c;
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byte unsigned d;
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reg [3:0] e;
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reg signed [3:0] f;
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struct packed {
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logic a;
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logic signed b;
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} x;
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struct packed signed {
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logic a;
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logic signed b;
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} y;
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} S;
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S s;
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initial begin
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// test codegen for LHS
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s.a = '1;
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s.b = '1;
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s.c = '1;
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s.d = '1;
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s.e = '1;
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s.f = '1;
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s.x.a = '1;
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s.x.b = '1;
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s.y.a = '1;
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s.y.b = '1;
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end
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`define CHECK(expr, width, signedness) \
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case (expr) \
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1'sb1: \
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case (expr) \
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2'sb11: if (!(signedness)) fail = 1; \
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default: if (signedness) fail = 1; \
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endcase \
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default: if (signedness) fail = 1; \
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endcase \
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case (expr) \
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1'b1: if ((width) != 1) fail = 1; \
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2'b11: if ((width) != 2) fail = 1; \
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3'b111: if ((width) != 3) fail = 1; \
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4'b1111: if ((width) != 4) fail = 1; \
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5'b1111_1: if ((width) != 5) fail = 1; \
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6'b1111_11: if ((width) != 6) fail = 1; \
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7'b1111_11: if ((width) != 7) fail = 1; \
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8'b1111_1111: if ((width) != 8) fail = 1; \
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9'b1111_1111_1: if ((width) != 9) fail = 1; \
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default: fail = 1; \
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endcase \
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begin \
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reg [9:0] indirect; \
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indirect = (expr); \
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if ((indirect != (expr)) != (signedness)) fail = 1; \
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indirect = $unsigned(expr); \
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if ($countones(indirect) != (width)) fail = 1; \
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end
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initial begin
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reg fail;
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fail = 0;
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`CHECK(s.a, 1, 0)
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`CHECK(s.b, 1, 1)
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`CHECK(s.c, 8, 1)
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`CHECK(s.d, 8, 0)
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`CHECK(s.e, 4, 0)
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`CHECK(s.f, 4, 1)
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`CHECK(s.x.a, 1, 0)
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`CHECK(s.x.b, 1, 1)
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`CHECK(s.y.a, 1, 0)
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`CHECK(s.y.b, 1, 1)
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// TODO(zachjs): support access to whole sub-structs and unions
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// `CHECK(s.x, 2, 0)
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// `CHECK(s.y, 2, 1)
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assert (fail === 0);
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end
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endmodule
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