mirror of https://github.com/YosysHQ/yosys.git
5 lines
194 B
Verilog
5 lines
194 B
Verilog
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module \$_DFFSRE_PPPP_ (input C, S, R, E, D, output Q);
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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dffepc #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.CLK(C), .PRE(S), .CLR(R), .EN(E), .D(D), .Q(Q));
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endmodule
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