2020-06-06 15:37:29 -05:00
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 whitequark <whitequark@whitequark.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef CXXRTL_VCD_H
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#define CXXRTL_VCD_H
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#include <backends/cxxrtl/cxxrtl.h>
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namespace cxxrtl {
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class vcd_writer {
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struct variable {
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size_t ident;
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size_t width;
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chunk_t *curr;
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cxxrtl: implement debug information outlining.
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.
This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.
Benchmarking a representative design (Minerva SoC SRAM) shows that:
* Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
* Switching from `-g1` to `-g2`, both used with `-O6`, increases
compile time by ~25%.
* Although `-g2` increases the resident size of generated modules,
this has no effect on runtime.
Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.
We'll have our cake and eat it too!
2020-12-13 01:03:16 -06:00
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size_t cache_offset;
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debug_outline *outline;
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bool *outline_warm;
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2020-06-06 15:37:29 -05:00
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};
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std::vector<std::string> current_scope;
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cxxrtl: implement debug information outlining.
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.
This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.
Benchmarking a representative design (Minerva SoC SRAM) shows that:
* Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
* Switching from `-g1` to `-g2`, both used with `-O6`, increases
compile time by ~25%.
* Although `-g2` increases the resident size of generated modules,
this has no effect on runtime.
Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.
We'll have our cake and eat it too!
2020-12-13 01:03:16 -06:00
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std::map<debug_outline*, bool> outlines;
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2020-06-06 15:37:29 -05:00
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std::vector<variable> variables;
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2020-06-06 16:55:53 -05:00
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std::vector<chunk_t> cache;
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2020-06-08 11:36:26 -05:00
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std::map<chunk_t*, size_t> aliases;
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2020-06-06 15:37:29 -05:00
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bool streaming = false;
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void emit_timescale(unsigned number, const std::string &unit) {
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assert(!streaming);
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assert(number == 1 || number == 10 || number == 100);
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assert(unit == "s" || unit == "ms" || unit == "us" ||
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unit == "ns" || unit == "ps" || unit == "fs");
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buffer += "$timescale " + std::to_string(number) + " " + unit + " $end\n";
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}
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void emit_scope(const std::vector<std::string> &scope) {
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assert(!streaming);
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while (current_scope.size() > scope.size() ||
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(current_scope.size() > 0 &&
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current_scope[current_scope.size() - 1] != scope[current_scope.size() - 1])) {
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buffer += "$upscope $end\n";
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current_scope.pop_back();
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}
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while (current_scope.size() < scope.size()) {
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buffer += "$scope module " + scope[current_scope.size()] + " $end\n";
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current_scope.push_back(scope[current_scope.size()]);
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}
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}
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void emit_ident(size_t ident) {
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do {
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buffer += '!' + ident % 94; // "base94"
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ident /= 94;
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} while (ident != 0);
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}
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2021-07-19 11:20:49 -05:00
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void emit_name(const std::string &name) {
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for (char c : name) {
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if (c == ':') {
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// Due to a bug, GTKWave cannot parse a colon in the variable name, causing the VCD file
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// to be unreadable. It cannot be escaped either, so replace it with the sideways colon.
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buffer += "..";
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} else {
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buffer += c;
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}
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}
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}
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2020-06-11 08:31:16 -05:00
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void emit_var(const variable &var, const std::string &type, const std::string &name,
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size_t lsb_at, bool multipart) {
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2020-06-06 15:37:29 -05:00
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assert(!streaming);
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buffer += "$var " + type + " " + std::to_string(var.width) + " ";
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emit_ident(var.ident);
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2021-07-19 11:20:49 -05:00
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buffer += " ";
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emit_name(name);
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2020-06-11 08:31:16 -05:00
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if (multipart || name.back() == ']' || lsb_at != 0) {
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if (var.width == 1)
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buffer += " [" + std::to_string(lsb_at) + "]";
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else
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buffer += " [" + std::to_string(lsb_at + var.width - 1) + ":" + std::to_string(lsb_at) + "]";
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}
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buffer += " $end\n";
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2020-06-06 15:37:29 -05:00
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}
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void emit_enddefinitions() {
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assert(!streaming);
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buffer += "$enddefinitions $end\n";
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streaming = true;
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}
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void emit_time(uint64_t timestamp) {
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assert(streaming);
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buffer += "#" + std::to_string(timestamp) + "\n";
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}
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void emit_scalar(const variable &var) {
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assert(streaming);
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assert(var.width == 1);
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buffer += (*var.curr ? '1' : '0');
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emit_ident(var.ident);
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buffer += '\n';
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}
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void emit_vector(const variable &var) {
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assert(streaming);
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buffer += 'b';
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for (size_t bit = var.width - 1; bit != (size_t)-1; bit--) {
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bool bit_curr = var.curr[bit / (8 * sizeof(chunk_t))] & (1 << (bit % (8 * sizeof(chunk_t))));
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buffer += (bit_curr ? '1' : '0');
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}
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buffer += ' ';
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emit_ident(var.ident);
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buffer += '\n';
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}
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cxxrtl: implement debug information outlining.
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.
This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.
Benchmarking a representative design (Minerva SoC SRAM) shows that:
* Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
* Switching from `-g1` to `-g2`, both used with `-O6`, increases
compile time by ~25%.
* Although `-g2` increases the resident size of generated modules,
this has no effect on runtime.
Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.
We'll have our cake and eat it too!
2020-12-13 01:03:16 -06:00
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void reset_outlines() {
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for (auto &outline_it : outlines)
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outline_it.second = /*warm=*/(outline_it.first == nullptr);
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}
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variable ®ister_variable(size_t width, chunk_t *curr, bool constant = false, debug_outline *outline = nullptr) {
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2020-06-08 11:36:26 -05:00
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if (aliases.count(curr)) {
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return variables[aliases[curr]];
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} else {
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cxxrtl: implement debug information outlining.
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.
This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.
Benchmarking a representative design (Minerva SoC SRAM) shows that:
* Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
* Switching from `-g1` to `-g2`, both used with `-O6`, increases
compile time by ~25%.
* Although `-g2` increases the resident size of generated modules,
this has no effect on runtime.
Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.
We'll have our cake and eat it too!
2020-12-13 01:03:16 -06:00
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auto outline_it = outlines.emplace(outline, /*warm=*/(outline == nullptr)).first;
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2020-06-08 11:36:26 -05:00
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const size_t chunks = (width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);
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aliases[curr] = variables.size();
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2020-06-10 09:39:45 -05:00
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if (constant) {
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cxxrtl: implement debug information outlining.
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.
This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.
Benchmarking a representative design (Minerva SoC SRAM) shows that:
* Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
* Switching from `-g1` to `-g2`, both used with `-O6`, increases
compile time by ~25%.
* Although `-g2` increases the resident size of generated modules,
this has no effect on runtime.
Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.
We'll have our cake and eat it too!
2020-12-13 01:03:16 -06:00
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variables.emplace_back(variable { variables.size(), width, curr, (size_t)-1, outline_it->first, &outline_it->second });
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2020-06-08 12:38:11 -05:00
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} else {
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cxxrtl: implement debug information outlining.
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.
This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.
Benchmarking a representative design (Minerva SoC SRAM) shows that:
* Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
* Switching from `-g1` to `-g2`, both used with `-O6`, increases
compile time by ~25%.
* Although `-g2` increases the resident size of generated modules,
this has no effect on runtime.
Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.
We'll have our cake and eat it too!
2020-12-13 01:03:16 -06:00
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variables.emplace_back(variable { variables.size(), width, curr, cache.size(), outline_it->first, &outline_it->second });
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2020-06-08 12:38:11 -05:00
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cache.insert(cache.end(), &curr[0], &curr[chunks]);
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}
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2020-06-08 11:36:26 -05:00
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return variables.back();
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}
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2020-06-06 16:55:53 -05:00
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}
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bool test_variable(const variable &var) {
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cxxrtl: implement debug information outlining.
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.
This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.
Benchmarking a representative design (Minerva SoC SRAM) shows that:
* Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
* Switching from `-g1` to `-g2`, both used with `-O6`, increases
compile time by ~25%.
* Although `-g2` increases the resident size of generated modules,
this has no effect on runtime.
Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.
We'll have our cake and eat it too!
2020-12-13 01:03:16 -06:00
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if (var.cache_offset == (size_t)-1)
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2020-06-10 09:39:45 -05:00
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return false; // constant
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cxxrtl: implement debug information outlining.
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.
This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.
Benchmarking a representative design (Minerva SoC SRAM) shows that:
* Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
* Switching from `-g1` to `-g2`, both used with `-O6`, increases
compile time by ~25%.
* Although `-g2` increases the resident size of generated modules,
this has no effect on runtime.
Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.
We'll have our cake and eat it too!
2020-12-13 01:03:16 -06:00
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if (!*var.outline_warm) {
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var.outline->eval();
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*var.outline_warm = true;
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}
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2020-06-06 16:55:53 -05:00
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const size_t chunks = (var.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);
|
cxxrtl: implement debug information outlining.
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.
This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.
Benchmarking a representative design (Minerva SoC SRAM) shows that:
* Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
* Switching from `-g1` to `-g2`, both used with `-O6`, increases
compile time by ~25%.
* Although `-g2` increases the resident size of generated modules,
this has no effect on runtime.
Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.
We'll have our cake and eat it too!
2020-12-13 01:03:16 -06:00
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if (std::equal(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset])) {
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2020-06-06 16:55:53 -05:00
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return false;
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} else {
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cxxrtl: implement debug information outlining.
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.
This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.
Benchmarking a representative design (Minerva SoC SRAM) shows that:
* Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
* Switching from `-g1` to `-g2`, both used with `-O6`, increases
compile time by ~25%.
* Although `-g2` increases the resident size of generated modules,
this has no effect on runtime.
Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.
We'll have our cake and eat it too!
2020-12-13 01:03:16 -06:00
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std::copy(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset]);
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2020-06-06 16:55:53 -05:00
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return true;
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}
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}
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2020-06-06 15:37:29 -05:00
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static std::vector<std::string> split_hierarchy(const std::string &hier_name) {
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|
|
|
std::vector<std::string> hierarchy;
|
|
|
|
size_t prev = 0;
|
|
|
|
while (true) {
|
2020-06-09 06:05:35 -05:00
|
|
|
size_t curr = hier_name.find_first_of(' ', prev);
|
|
|
|
if (curr == std::string::npos) {
|
|
|
|
hierarchy.push_back(hier_name.substr(prev));
|
2020-06-06 15:37:29 -05:00
|
|
|
break;
|
2020-06-09 06:05:35 -05:00
|
|
|
} else {
|
|
|
|
hierarchy.push_back(hier_name.substr(prev, curr - prev));
|
|
|
|
prev = curr + 1;
|
|
|
|
}
|
2020-06-06 15:37:29 -05:00
|
|
|
}
|
|
|
|
return hierarchy;
|
|
|
|
}
|
|
|
|
|
|
|
|
public:
|
|
|
|
std::string buffer;
|
|
|
|
|
|
|
|
void timescale(unsigned number, const std::string &unit) {
|
|
|
|
emit_timescale(number, unit);
|
|
|
|
}
|
|
|
|
|
2020-06-11 08:31:16 -05:00
|
|
|
void add(const std::string &hier_name, const debug_item &item, bool multipart = false) {
|
2020-06-06 15:37:29 -05:00
|
|
|
std::vector<std::string> scope = split_hierarchy(hier_name);
|
|
|
|
std::string name = scope.back();
|
|
|
|
scope.pop_back();
|
|
|
|
|
|
|
|
emit_scope(scope);
|
|
|
|
switch (item.type) {
|
|
|
|
// Not the best naming but oh well...
|
|
|
|
case debug_item::VALUE:
|
2020-06-11 08:31:16 -05:00
|
|
|
emit_var(register_variable(item.width, item.curr, /*constant=*/item.next == nullptr),
|
|
|
|
"wire", name, item.lsb_at, multipart);
|
2020-06-06 15:37:29 -05:00
|
|
|
break;
|
|
|
|
case debug_item::WIRE:
|
2020-06-11 08:31:16 -05:00
|
|
|
emit_var(register_variable(item.width, item.curr),
|
|
|
|
"reg", name, item.lsb_at, multipart);
|
2020-06-06 15:37:29 -05:00
|
|
|
break;
|
|
|
|
case debug_item::MEMORY: {
|
|
|
|
const size_t stride = (item.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);
|
|
|
|
for (size_t index = 0; index < item.depth; index++) {
|
|
|
|
chunk_t *nth_curr = &item.curr[stride * index];
|
|
|
|
std::string nth_name = name + '[' + std::to_string(index) + ']';
|
2020-06-11 08:31:16 -05:00
|
|
|
emit_var(register_variable(item.width, nth_curr),
|
|
|
|
"reg", nth_name, item.lsb_at, multipart);
|
2020-06-06 15:37:29 -05:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2020-06-10 09:39:45 -05:00
|
|
|
case debug_item::ALIAS:
|
|
|
|
// Like VALUE, but, even though `item.next == nullptr` always holds, the underlying value
|
|
|
|
// can actually change, and must be tracked. In most cases the VCD identifier will be
|
|
|
|
// unified with the aliased reg, but we should handle the case where only the alias is
|
|
|
|
// added to the VCD writer, too.
|
2020-06-11 08:31:16 -05:00
|
|
|
emit_var(register_variable(item.width, item.curr),
|
|
|
|
"wire", name, item.lsb_at, multipart);
|
2020-06-10 09:39:45 -05:00
|
|
|
break;
|
cxxrtl: implement debug information outlining.
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.
This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.
Benchmarking a representative design (Minerva SoC SRAM) shows that:
* Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
* Switching from `-g1` to `-g2`, both used with `-O6`, increases
compile time by ~25%.
* Although `-g2` increases the resident size of generated modules,
this has no effect on runtime.
Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.
We'll have our cake and eat it too!
2020-12-13 01:03:16 -06:00
|
|
|
case debug_item::OUTLINE:
|
|
|
|
emit_var(register_variable(item.width, item.curr, /*constant=*/false, item.outline),
|
|
|
|
"wire", name, item.lsb_at, multipart);
|
|
|
|
break;
|
2020-06-06 15:37:29 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
template<class Filter>
|
|
|
|
void add(const debug_items &items, const Filter &filter) {
|
|
|
|
// `debug_items` is a map, so the items are already sorted in an order optimal for emitting
|
|
|
|
// VCD scope sections.
|
2020-06-11 08:31:16 -05:00
|
|
|
for (auto &it : items.table)
|
|
|
|
for (auto &part : it.second)
|
|
|
|
if (filter(it.first, part))
|
|
|
|
add(it.first, part, it.second.size() > 1);
|
2020-06-06 15:37:29 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
void add(const debug_items &items) {
|
2021-01-26 11:42:23 -06:00
|
|
|
this->add(items, [](const std::string &, const debug_item &) {
|
2020-06-06 15:37:29 -05:00
|
|
|
return true;
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
|
|
|
void add_without_memories(const debug_items &items) {
|
2021-01-26 11:42:23 -06:00
|
|
|
this->add(items, [](const std::string &, const debug_item &item) {
|
2020-06-10 09:39:45 -05:00
|
|
|
return item.type != debug_item::MEMORY;
|
2020-06-06 15:37:29 -05:00
|
|
|
});
|
|
|
|
}
|
|
|
|
|
|
|
|
void sample(uint64_t timestamp) {
|
2020-06-06 16:55:53 -05:00
|
|
|
bool first_sample = !streaming;
|
|
|
|
if (first_sample) {
|
2020-06-06 15:37:29 -05:00
|
|
|
emit_scope({});
|
|
|
|
emit_enddefinitions();
|
|
|
|
}
|
cxxrtl: implement debug information outlining.
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.
This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.
Benchmarking a representative design (Minerva SoC SRAM) shows that:
* Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
* Switching from `-g1` to `-g2`, both used with `-O6`, increases
compile time by ~25%.
* Although `-g2` increases the resident size of generated modules,
this has no effect on runtime.
Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.
We'll have our cake and eat it too!
2020-12-13 01:03:16 -06:00
|
|
|
reset_outlines();
|
2020-06-06 15:37:29 -05:00
|
|
|
emit_time(timestamp);
|
2020-06-06 16:55:53 -05:00
|
|
|
for (auto var : variables)
|
|
|
|
if (test_variable(var) || first_sample) {
|
|
|
|
if (var.width == 1)
|
|
|
|
emit_scalar(var);
|
|
|
|
else
|
|
|
|
emit_vector(var);
|
|
|
|
}
|
2020-06-06 15:37:29 -05:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|