yosys/tests/techmap/clkbufmap.ys

read_verilog <<EOT
module clkbuf (input i, (* clkbuf_driver *) output o); endmodule
module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule
module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule
module latch (input e, d, output q); endmodule

module top(input clk1, clk2, clk3, d, e, output [2:0] q);
dff s0 (.clk(clk1), .d(d), .q(q[0]));
dffe s1 (.c(clk2), .d(d), .e(e), .q(q[1]));
latch s2 (.e(clk3), .d(d), .q(q[2]));
endmodule
EOT

hierarchy -auto-top
design -save ref

# ----------------------

design -load ref
clkbufmap -buf clkbuf o:i
select -assert-count 1 w:clk1 %a %co t:clkbuf %i
select -assert-count 1 w:clk2 %a %co t:clkbuf %i
select -assert-count 2 t:clkbuf

# ----------------------

design -load ref
setattr -set clkbuf_inhibit 0 w:clk1
setattr -set clkbuf_inhibit 1 w:clk2
clkbufmap -buf clkbuf o:i
select -assert-count 1 w:clk1 %a %co t:clkbuf %i
select -assert-count 0 w:clk2 %a %co t:clkbuf %i
select -assert-count 1 t:clkbuf

# ----------------------

design -load ref
setattr -set clkbuf_inhibit 1 w:clk1
setattr -set buffer_type "bufg" w:clk2
clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
select -assert-count 1 w:clk1 %a %co t:clkbuf %i
select -assert-count 1 w:clk2 %a %co t:clkbuf %i
select -assert-count 2 t:clkbuf

# ----------------------

design -load ref
setattr -set buffer_type "none" w:clk1
setattr -set buffer_type "bufr" w:clk2
clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
select -assert-count 0 w:clk1 %a %co t:clkbuf %i
select -assert-count 0 w:clk2 %a %co t:clkbuf %i
select -assert-count 0 t:clkbuf