mirror of https://github.com/YosysHQ/yosys.git
57 lines
1.1 KiB
Verilog
57 lines
1.1 KiB
Verilog
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module \$__NX_PDPSC512K (CLK2, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 14;
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parameter CFG_DBITS = 32;
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parameter CFG_ENABLE_A = 4;
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parameter CLKPOL2 = 1;
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parameter [524287:0] INIT = 524287'b0;
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input CLK2;
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input [CFG_ABITS-1:0] A1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input [CFG_ENABLE_A-1:0] A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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output [CFG_DBITS-1:0] B1DATA;
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input B1EN;
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wire clk;
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wire [31:0] rd;
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assign B1DATA = rd[CFG_DBITS-1:0];
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generate
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if (CLKPOL2)
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assign clk = CLK2;
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else
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INV clk_inv_i (.A(CLK2), .Z(clk));
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endgenerate
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wire we = |A1EN;
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localparam INIT_CHUNK_SIZE = 4096;
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function [5119:0] permute_init;
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input [INIT_CHUNK_SIZE-1:0] chunk;
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integer i;
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begin
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for (i = 0; i < 128; i = i + 1'b1)
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permute_init[i * 40 +: 40] = {8'b0, chunk[i * 32 +: 32]};
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end
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endfunction
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generate
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PDPSC512K #(
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.OUTREG("NO_REG"),
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.ECC_BYTE_SEL("BYTE_EN"),
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`include "lrams_init.vh"
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.GSR("DISABLED")
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) _TECHMAP_REPLACE_ (
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.CLK(clk), .RSTR(1'b0),
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.DI(A1DATA), .ADW(A1ADDR), .CEW(we), .WE(we), .CSW(1'b1),
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.ADR(B1ADDR), .DO(rd), .CER(B1EN), .CSR(1'b1),
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);
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endgenerate
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endmodule
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