yosys/tests/opt/opt_ff_sat.v

module top (
	input clk,
	output reg [7:0] cnt
);
	initial cnt = 0;
	always @(posedge clk) begin
		if (cnt < 20)
			cnt <= cnt + 1;
		else
			cnt <= 0;
	end
endmodule
Refactor "opt_rmdff -sat" Signed-off-by: Clifford Wolf <clifford@clifford.at> 2019-06-20 06:44:21 -05:00			`module top (`
			`input clk,`
			`output reg [7:0] cnt`
			`);`
			`initial cnt = 0;`
			`always @(posedge clk) begin`
			`if (cnt < 20)`
			`cnt <= cnt + 1;`
			`else`
			`cnt <= 0;`
			`end`
Optimizing DFFs whose initial value prevents their value from changing This is a proof of concept implementation that invokes SAT solver via Pass::call method. 2019-05-28 01:48:21 -05:00			`endmodule`