yosys/tests/various/logger_warn.ys

mirror of https://github.com/YosysHQ/yosys.git
logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1
read_verilog << EOF
module top(...);
	assign b = w;
endmodule
EOF
Added back tests for logger 2020-03-13 09:00:18 -05:00			`logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1`
			`read_verilog << EOF`
			`module top(...);`
			`assign b = w;`
			`endmodule`
			`EOF`