mirror of https://github.com/YosysHQ/yosys.git
26 lines
544 B
Verilog
26 lines
544 B
Verilog
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module forloops01 (input clk, a, b, output reg [3:0] p, q, x, y);
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integer k;
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always @(posedge clk) begin
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for (k=0; k<2; k=k+1)
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p[2*k +: 2] = {a, b} ^ {2{k}};
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x <= k + {a, b};
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end
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always @* begin
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for (k=0; k<4; k=k+1)
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q[k] = {~a, ~b, a, b} >> k[1:0];
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y = k - {a, b};
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end
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endmodule
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module forloops02 (input clk, a, b, output reg [3:0] q, x, output [3:0] y);
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integer k;
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always @* begin
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for (k=0; k<4; k=k+1)
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q[k] = {~a, ~b, a, b} >> k[1:0];
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end
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always @* begin
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x = k + {a, b};
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end
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assign y = k - {a, b};
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endmodule
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