mirror of https://github.com/YosysHQ/yosys.git
24 lines
669 B
Verilog
24 lines
669 B
Verilog
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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localparam rep = 1<<(4-WIDTH);
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wire [3:0] I;
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generate
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if(WIDTH == 2) begin
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assign I = {1'b0, 1'b0, A[1], A[0]};
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end else if(WIDTH == 3) begin
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assign I = {1'b0, A[2], A[1], A[0]};
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end else if(WIDTH == 4) begin
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assign I = {A[3], A[2], A[1], A[0]};
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end
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endgenerate
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LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .F(Y));
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endmodule
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module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .D(D), .Q(Q)); endmodule
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