yosys/manual/PRESENTATION_ExAdv/macc_simple_test.v

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2014-02-20 05:46:29 -06:00
module test(a, b, c, d, y);
input [15:0] a, b;
input [31:0] c, d;
output [31:0] y;
assign y = a * b + c + d;
endmodule