mirror of https://github.com/YosysHQ/yosys.git
18 lines
214 B
Plaintext
18 lines
214 B
Plaintext
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bram $__TRELLIS_DPR16X4
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init 1
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abits 4
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dbits 4
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 0 0
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clocks 0 1
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clkpol 0 2
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endbram
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match $__TRELLIS_DPR16X4
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make_outreg
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min wports 1
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endmatch
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