mirror of https://github.com/YosysHQ/yosys.git
16 lines
219 B
Coq
16 lines
219 B
Coq
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module top(
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input clk,
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input a,
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output b
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);
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reg b_reg;
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initial begin
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b_reg <= 0;
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end
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assign b = b_reg;
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always @(posedge clk) begin
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b_reg <= a && b_reg;
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end
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endmodule
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