yosys/tests/xilinx/mux.ys

read_verilog mux.v
design -save read

proc
hierarchy -top mux2
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3

select -assert-none t:LUT3 %% t:* %D


design -load read
proc
hierarchy -top mux4
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT6

select -assert-none t:LUT6 %% t:* %D


design -load read
proc
hierarchy -top mux8
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
select -assert-count 2 t:LUT6

select -assert-none t:LUT3 t:LUT6 %% t:* %D


design -load read
proc
hierarchy -top mux16
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 5 t:LUT6

select -assert-none t:LUT6 %% t:* %D