mirror of https://github.com/YosysHQ/yosys.git
151 lines
2.9 KiB
Coq
151 lines
2.9 KiB
Coq
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module IBUF(O, I);
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output O;
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input I;
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assign O = I;
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endmodule
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module OBUF(O, I);
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output O;
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input I;
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assign O = I;
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endmodule
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module BUFGP(O, I);
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output O;
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input I;
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assign O = I;
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endmodule
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module OBUFT(O, I, T);
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output O;
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input I, T;
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assign O = T ? 1'bz : I;
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endmodule
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module GND(G);
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output G;
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assign G = 0;
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endmodule
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module INV(O, I);
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input I;
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output O;
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assign O = !I;
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endmodule
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module LUT1(O, I0);
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parameter [1:0] INIT = 0;
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input I0;
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output O;
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assign O = I0 ? INIT[1] : INIT[0];
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endmodule
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module LUT2(O, I0, I1);
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parameter [3:0] INIT = 0;
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input I0, I1;
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output O;
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wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT3(O, I0, I1, I2);
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parameter [7:0] INIT = 0;
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input I0, I1, I2;
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output O;
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wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT4(O, I0, I1, I2, I3);
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parameter [15:0] INIT = 0;
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input I0, I1, I2, I3;
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output O;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT5(O, I0, I1, I2, I3, I4);
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parameter [31:0] INIT = 0;
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input I0, I1, I2, I3, I4;
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output O;
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wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT6(O, I0, I1, I2, I3, I4, I5);
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parameter [63:0] INIT = 0;
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input I0, I1, I2, I3, I4, I5;
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output O;
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wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
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wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module MUXCY(O, CI, DI, S);
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input CI, DI, S;
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output O;
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assign O = S ? CI : DI;
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endmodule
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module MUXF7(O, I0, I1, S);
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input I0, I1, S;
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output O;
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assign O = S ? I1 : I0;
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endmodule
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module MUXF8(O, I0, I1, S);
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input I0, I1, S;
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output O;
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assign O = S ? I1 : I0;
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endmodule
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module VCC(P);
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output P;
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assign P = 1;
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endmodule
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module XORCY(O, CI, LI);
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input CI, LI;
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output O;
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assign O = CI ^ LI;
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endmodule
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module CARRY4(CO, O, CI, CYINIT, DI, S);
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output [3:0] CO, O;
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input CI, CYINIT;
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input [3:0] DI, S;
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wire ci_or_cyinit;
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assign O = S ^ {CO[2:0], ci_or_cyinit};
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assign CO[0] = S[0] ? ci_or_cyinit : DI[0];
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assign CO[1] = S[1] ? CO[0] : DI[1];
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assign CO[2] = S[2] ? CO[1] : DI[2];
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assign CO[3] = S[3] ? CO[2] : DI[3];
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assign ci_or_cyinit = CI | CYINIT;
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endmodule
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/*
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module FDRE (Q, C, CR, D, R);
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parameter [0:0] INIT = 1'b0,
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parameter [0:0] IS_C_INVERTED = 1'b0,
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parameter [0:0] IS_D_INVERTED = 1'b0,
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parameter [0:0] IS_R_INVERTED = 1'b0
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output Q;
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input C;
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input CE;
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input D;
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input R;
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// -- FIXME --
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endmodule
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*/
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