mirror of https://github.com/YosysHQ/yosys.git
43 lines
890 B
Verilog
43 lines
890 B
Verilog
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//-----------------------------------------------------
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// Design Name : rom_using_case
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// File Name : rom_using_case.v
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// Function : ROM using case
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module rom_using_case (
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address , // Address input
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data , // Data output
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read_en , // Read Enable
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ce // Chip Enable
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);
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input [3:0] address;
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output [7:0] data;
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input read_en;
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input ce;
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reg [7:0] data ;
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always @ (ce or read_en or address)
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begin
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case (address)
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0 : data = 10;
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1 : data = 55;
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2 : data = 244;
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3 : data = 0;
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4 : data = 1;
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5 : data = 8'hff;
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6 : data = 8'h11;
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7 : data = 8'h1;
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8 : data = 8'h10;
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9 : data = 8'h0;
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10 : data = 8'h10;
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11 : data = 8'h15;
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12 : data = 8'h60;
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13 : data = 8'h90;
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14 : data = 8'h70;
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15 : data = 8'h90;
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endcase
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end
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endmodule
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