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12 lines
241 B
Systemverilog
12 lines
241 B
Systemverilog
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module top (input clk, a, b);
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always @(posedge clk) begin
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if (a);
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else assume property (@(posedge clk) b);
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end
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`ifndef FAIL
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assume property (@(posedge clk) !a);
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`endif
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assert property (@(posedge clk) b);
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endmodule
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