mirror of https://github.com/YosysHQ/yosys.git
50 lines
929 B
Systemverilog
50 lines
929 B
Systemverilog
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// Test multidimensional packed arrays
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typedef logic [0:3][7:0] reg2dim_t;
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typedef logic [7:0] reg8_t;
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typedef reg8_t [0:3] reg2dim1_t;
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module pcktest1 (
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input logic clk,
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input logic [0:3][7:0] in,
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input logic [1:0] ix,
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output reg8_t out
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);
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always_ff @(posedge clk) begin
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out <= in[ix];
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end
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endmodule
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module pcktest2 (
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input logic clk,
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input reg8_t [0:3] in,
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input logic [1:0] ix,
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output reg8_t out
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);
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always_ff @(posedge clk) begin
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out <= in[ix];
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end
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endmodule
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module pcktest3 (
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input logic clk,
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input reg2dim_t in,
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input logic [1:0] ix,
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output reg8_t out
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);
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always_ff @(posedge clk) begin
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out <= in[ix];
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end
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endmodule
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module pcktest4 (
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input logic clk,
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input reg2dim1_t in,
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input logic [1:0] ix,
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output reg8_t out
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);
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always_ff @(posedge clk) begin
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out <= in[ix];
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end
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endmodule
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