mirror of https://github.com/YosysHQ/yosys.git
7 lines
65 B
Verilog
7 lines
65 B
Verilog
|
module a;
|
||
|
wire [5:0]x;
|
||
|
wire [3:0]y;
|
||
|
assign y = (4)55;
|
||
|
endmodule
|
||
|
|