mirror of https://github.com/YosysHQ/yosys.git
13 lines
215 B
Coq
13 lines
215 B
Coq
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module uut_always01(clock, reset, c3, c2, c1, c0);
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input clock, reset;
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output c3, c2, c1, c0;
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reg [3:0] count;
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assign {c3, c2, c1, c0} = count;
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always @(posedge clock)
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count <= reset ? 0 : count + 1;
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endmodule
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