mirror of https://github.com/YosysHQ/yosys.git
84 lines
2.6 KiB
C++
84 lines
2.6 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct EquivRemovePass : public Pass {
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EquivRemovePass() : Pass("equiv_remove", "remove $equiv cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" equiv_remove [options] [selection]\n");
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log("\n");
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log("This command removes the selected $equiv cells. If neither -gold nor -gate is\n");
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log("used then only proven cells are removed.\n");
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log("\n");
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log(" -gold\n");
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log(" keep gold circuit\n");
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log("\n");
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log(" -gate\n");
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log(" keep gate circuit\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, Design *design)
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{
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bool mode_gold = false;
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bool mode_gate = false;
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int remove_count = 0;
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log_header("Executing EQUIV_REMOVE pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-gold") {
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mode_gold = true;
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continue;
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}
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if (args[argidx] == "-gate") {
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mode_gate = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (mode_gold && mode_gate)
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log_cmd_error("Options -gold and -gate are exclusive.\n");
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for (auto module : design->selected_modules())
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{
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for (auto cell : module->selected_cells())
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if (cell->type == "$equiv" && (mode_gold || mode_gate || cell->getPort("\\A") == cell->getPort("\\B"))) {
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log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort("\\Y")));
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module->connect(cell->getPort("\\Y"), mode_gate ? cell->getPort("\\B") : cell->getPort("\\A"));
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module->remove(cell);
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remove_count++;
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}
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}
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log("Removed a total of %d $equiv cells.\n", remove_count);
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}
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} EquivRemovePass;
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PRIVATE_NAMESPACE_END
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