yosys/tests/sat/asserts_seq.ys

read_verilog -sv asserts_seq.v
hierarchy; proc; opt; async2sync

sat -verify  -prove-asserts -tempinduct -seq 1 test_001
sat -falsify -prove-asserts -tempinduct -seq 1 test_002
sat -falsify -prove-asserts -tempinduct -seq 1 test_003
sat -falsify -prove-asserts -tempinduct -seq 1 test_004
sat -verify  -prove-asserts -tempinduct -seq 1 test_005

sat -verify  -prove-asserts -seq 2 test_001
sat -falsify -prove-asserts -seq 2 test_002
sat -falsify -prove-asserts -seq 2 test_003
sat -falsify -prove-asserts -seq 2 test_004
sat -verify  -prove-asserts -seq 2 test_005
Added read_verilog -sv options, added support for bit, logic, allways_ff, always_comb, and always_latch 2014-06-12 04:54:20 -05:00			`read_verilog -sv asserts_seq.v`
tests: Run async2sync before sat and/or sim to handle $check cells Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions. 2024-01-22 10:44:05 -06:00			`hierarchy; proc; opt; async2sync`
Added test cases for sat command 2014-02-04 06:43:34 -06:00
			`sat -verify -prove-asserts -tempinduct -seq 1 test_001`
			`sat -falsify -prove-asserts -tempinduct -seq 1 test_002`
			`sat -falsify -prove-asserts -tempinduct -seq 1 test_003`
			`sat -falsify -prove-asserts -tempinduct -seq 1 test_004`
			`sat -verify -prove-asserts -tempinduct -seq 1 test_005`

			`sat -verify -prove-asserts -seq 2 test_001`
			`sat -falsify -prove-asserts -seq 2 test_002`
			`sat -falsify -prove-asserts -seq 2 test_003`
			`sat -falsify -prove-asserts -seq 2 test_004`
			`sat -verify -prove-asserts -seq 2 test_005`