mirror of https://github.com/YosysHQ/yosys.git
9 lines
384 B
Plaintext
9 lines
384 B
Plaintext
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read_verilog ../common/logic.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 8 t:LUT4
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select -assert-none t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D
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