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51 lines
1.6 KiB
ReStructuredText
51 lines
1.6 KiB
ReStructuredText
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.. role:: verilog(code)
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:language: Verilog
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Unary operators
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---------------
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All unary RTL cells have one input port ``A`` and one output port ``Y``. They
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also have the following parameters:
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``A_SIGNED``
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Set to a non-zero value if the input ``A`` is signed and therefore should be
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sign-extended when needed.
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``A_WIDTH``
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The width of the input port ``A``.
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``Y_WIDTH``
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The width of the output port ``Y``.
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.. table:: Cell types for unary operators with their corresponding Verilog expressions.
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================== ==============
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Verilog Cell Type
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================== ==============
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:verilog:`Y = ~A` `$not`
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:verilog:`Y = +A` `$pos`
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:verilog:`Y = -A` `$neg`
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:verilog:`Y = &A` `$reduce_and`
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:verilog:`Y = |A` `$reduce_or`
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:verilog:`Y = ^A` `$reduce_xor`
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:verilog:`Y = ~^A` `$reduce_xnor`
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:verilog:`Y = |A` `$reduce_bool`
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:verilog:`Y = !A` `$logic_not`
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================== ==============
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For the unary cells that output a logical value (`$reduce_and`, `$reduce_or`,
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`$reduce_xor`, `$reduce_xnor`, `$reduce_bool`, `$logic_not`), when the
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``Y_WIDTH`` parameter is greater than 1, the output is zero-extended, and only
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the least significant bit varies.
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Note that `$reduce_or` and `$reduce_bool` actually represent the same logic
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function. But the HDL frontends generate them in different situations. A
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`$reduce_or` cell is generated when the prefix ``|`` operator is being used. A
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`$reduce_bool` cell is generated when a bit vector is used as a condition in an
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``if``-statement or ``?:``-expression.
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.. autocellgroup:: unary
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:members:
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:source:
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:linenos:
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