yosys/tests/ice40/mux.ys

read_verilog mux.v
proc
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40
design -load postopt
cd top
select -assert-count 19 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
Fix all comments from PR 2019-08-21 13:52:07 -05:00			`read_verilog mux.v`
Remove tech independent synthesis 2019-08-22 14:30:49 -05:00			`proc`
			`flatten`
Fix tests; Remove simulation; - Add -map and -assert options for equiv_opt; !!! '-assert' option was commented for the next tests (unproven $equiv cells was found): - dffs; - div_mod; - latches; - mul_pow; - Add design -load; - Remove simulations; 2019-08-20 07:52:25 -05:00			`equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40`
			`design -load postopt`
Remove tech independent synthesis 2019-08-22 14:30:49 -05:00			`cd top`
			`select -assert-count 19 t:SB_LUT4`
			`select -assert-none t:SB_LUT4 %% t:* %D`