mirror of https://github.com/YosysHQ/yosys.git
83 lines
2.4 KiB
Python
83 lines
2.4 KiB
Python
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import os
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import subprocess
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if not os.path.exists("work_ff"):
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os.mkdir("work_ff")
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modules = []
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with open("../cells_ff.vh", "r") as f:
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with open("work_ff/cells_ff_gate.v", "w") as g:
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for line in f:
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if not line.startswith("module"):
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g.write(line)
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continue
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else:
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spidx = line.find(" ")
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bridx = line.find("(")
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modname = line[spidx+1 : bridx]
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g.write("module %s_gate" % modname)
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g.write(line[bridx:])
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inpidx = line.find("input ")
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outpidx = line.find(", output")
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modules.append((modname, [x.strip() for x in line[inpidx+6:outpidx].split(",")]))
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with open("work_ff/testbench.v", "w") as f:
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print("""
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`timescale 1ns/ 1ps
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module testbench;
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reg pur = 0, clk, rst, cen, d;
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// Needed for Diamond sim models
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GSR GSR_INST (.GSR(1'b1));
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PUR PUR_INST (.PUR(pur));
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initial begin
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$dumpfile("work_ff/ffs.vcd");
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$dumpvars(0, testbench);
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#5;
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pur = 1;
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#95;
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repeat (2500) begin
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{clk, rst, cen, d} = $random;
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#10;
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check_outputs;
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#1;
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end
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$finish;
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end
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""", file=f)
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for modname, inputs in modules:
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print(" wire %s_gold_q, %s_gate_q;" % (modname, modname), file=f)
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portconns = []
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for inp in inputs:
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if inp in ("SCLK", "CK"):
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portconns.append(".%s(clk)" % inp)
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elif inp in ("CD", "PD"):
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portconns.append(".%s(rst)" % inp)
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elif inp == "SP":
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portconns.append(".%s(cen)" % inp)
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elif inp == "D":
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portconns.append(".%s(d)" % inp)
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else:
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assert False
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portconns.append(".Q(%s_gold_q)" % modname)
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print(" %s %s_gold_i (%s);" % (modname, modname, ", ".join(portconns)), file=f)
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portconns[-1] = (".Q(%s_gate_q)" % modname)
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print(" %s_gate %s_gate_i (%s);" % (modname, modname, ", ".join(portconns)), file=f)
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print("", file=f)
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print(" task check_outputs;", file=f)
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print(" begin", file=f)
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print(" if (%s_gold_q != %s_gate_q) $display(\"MISMATCH at %%1t: %s_gold_q=%%b, %s_gate_q=%%b\", $time, %s_gold_q, %s_gate_q);" %
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(modname, modname, modname, modname, modname, modname), file=f)
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print(" end", file=f)
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print(" endtask", file=f)
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print("endmodule", file=f)
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diamond_models = "/usr/local/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u"
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subprocess.call(["iverilog", "-s", "testbench", "-o", "work_ff/testbench", "-Dmixed_hdl", "-DNO_INCLUDES", "-y", diamond_models, "work_ff/cells_ff_gate.v", "../cells_sim.v", "work_ff/testbench.v"])
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subprocess.call(["vvp", "work_ff/testbench"])
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