mirror of https://github.com/YosysHQ/yosys.git
27 lines
450 B
VHDL
27 lines
450 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity top is
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port (
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clock : in std_logic;
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ctrl : in std_logic;
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x : out std_logic
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);
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end entity;
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architecture rtl of top is
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signal read : std_logic;
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signal write : std_logic;
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signal ready : std_logic;
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begin
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process (clock) begin
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if (rising_edge(clock)) then
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read <= not ctrl;
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write <= ctrl;
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ready <= write;
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end if;
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end process;
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x <= read xor write xor ready;
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end architecture;
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